LDPC Decoder Architecture for Variable Block Size Support
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Solution Overview
Problem
Current methods for using low-density parity-check (LDPC) codes face challenges with large block size support, intermediate block size support, and hardware complexity due to the need for multiple architectures for various code block lengths, leading to inefficiencies in data transmission and increased power consumption.
Innovation Solution
The system and method involve choosing optimal block sizes for transmission to maximize the minimum transmitted size, using techniques like puncturing, shortening, and repeating to derive intermediate code block lengths, and employing a common decoder architecture for different code rates and block sizes to reduce hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple LDPC code architectures are implemented to support various code block lengths, then support for different block sizes is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal LDPC decoder architecture that can handle multiple code block lengths (120, 240, 360, 480, 600 bits) through a single multi-functional design. The decoder uses configurable parameters and a unified structure that adapts to different block sizes, eliminating the need for separate dedicated decoders for each length while maintaining full support for all required block sizes.
2Adaptability or versatility
If data is transmitted in smaller packets, then adaptability to different data sizes is improved, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the code block length parameter based on the amount of data to be transmitted. The system can select from multiple standardized block sizes (120, 240, 360, 480, 600 bits) to optimize the balance between transmission flexibility and power efficiency. By changing the block size parameter rather than using fixed small packets, the system achieves adaptability while minimizing power consumption through more efficient error correction performance at larger block sizes.
3Use of energy by moving object
If larger code block sizes are used, then power consumption is reduced, but support for small data transmissions is limited
Solution Approach 1:
The patent segments the code block size support into multiple standardized sizes (120, 240, 360, 480, 600 bits) that can be selected based on transmission requirements. This segmentation allows the system to use larger blocks for bulk data transmission (reducing power consumption) while still supporting smaller blocks for brief data transmissions, achieving both power efficiency and adaptability through a family of standardized block sizes rather than a single size.
Data Source
AI summary
The present invention provides a low density parity check (LDPC) code system and method of using such a system. A transmitted LDPC code block size may be chosen such that the minimum transmitted block size is minimized. Further, the system provides for intermediate LDPC code block size support. Finally, a common decoder architecture may be used to decode different LDPC code rates and block sizes.