LDPC Memory Decoding With Threshold LLR Reset for Clipping Errors

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Solution Overview

Problem

Low-density parity check (LDPC) codes used in semiconductor memory devices face inefficiencies in decoding due to clipping errors, particularly in serial decoding methods, which affect decoding efficiency and error rate characteristics.

Innovation Solution

The proposed semiconductor memory device employs a decoding method that uses the Sum-Product algorithm with a threshold-based approach, where posterior log likelihood ratios (LLRs) are either updated or used as-is based on their absolute value, and includes a scheduler to control iterative processing, minimizing the impact of clipping errors by avoiding updates when LLRs exceed a predetermined threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If serial decoding using the Sum-Product algorithm is employed, then convergence speed is improved and memory consumption is reduced, but clipping errors occur when posterior LLRs exceed a predetermined threshold, degrading decoding efficiency and error rate characteristics

Engineering Contradiction:
Improveconvergence speedVSAvoiddecoding efficiency
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the posterior log likelihood ratio (LLR) values based on a threshold comparison. When the absolute value of a posterior LLR exceeds a predetermined threshold, the patent clips the value to the threshold; otherwise, it retains the original value. This parameter transformation resolves the contradiction by preventing clipping errors that degrade decoding efficiency while maintaining the fast convergence and low memory consumption benefits of serial decoding.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If the Min-Sum algorithm is used for row operations, then nonlinear function calculations are simplified, but large amounts of operations are still required, increasing computational complexity

Engineering Contradiction:
Improvecomputational complexityVSAvoiddecoding speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent transforms the computational approach by changing the parameter representation and operation method. Instead of performing complex nonlinear function calculations for each element, the patent uses a threshold-based clipping operation on posterior LLRs. This parameter transformation significantly reduces computational complexity while maintaining decoding speed, as the clipping operation is much simpler than traditional nonlinear function calculations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8751895B2Semiconductor memory device and decoding method
Publication Date: 2014.06.10 KIOXIA CORP
  • US8751895B2 patent drawing
  • US8751895B2 patent drawing
  • US8751895B2 patent drawing

AI summary

A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”