LDPC Layered Decoding with Delayed VN Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing layered decoding methods for Low-Density Parity-Check (LDPC) codes suffer from high decoding latency due to sequential memory access and processing, which can be exacerbated by the need for orthogonal row layers, leading to inefficiencies in hardware utilization and potential performance degradation in block-error rate.
Innovation Solution
The proposed fast layered decoding method allows simultaneous memory access and computation by delaying the update of Variable Node (VN) soft information by at least one layer, eliminating the requirement for orthogonal row layers and optimizing the use of decoding hardware, while adjusting Log-Likelihood Ratios (LLRs) to account for non-orthogonal rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential memory access and processing is used in existing layered decoding methods, then decoding can be performed with standard hardware, but decoding latency becomes high
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing check node messages in memory before they are needed for variable node updates. This allows the decoding process to proceed in parallel stages where memory access and computation occur simultaneously, eliminating sequential waiting time and reducing overall decoding latency.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing the decoding process into independent stages that can execute concurrently. By separating memory access operations from computation operations in the time domain, the system achieves overlapping execution that effectively reduces the critical path length and decoding latency.
2Productivity
If orthogonal row layers are enforced to enable layered decoding, then hardware utilization improves, but block-error rate performance degrades
Solution Approach 1:
The patent uses an intermediary approach by introducing a buffer memory that decouples the requirements for orthogonal layers. This buffer allows non-orthogonal layer structures to be used while still enabling efficient hardware utilization, as the memory buffer absorbs the dependencies between non-orthogonal layers without preventing parallel processing.
Solution Approach 2:
The patent changes the parameter of layer orthogonality from a strict requirement to an optional feature. By allowing non-orthogonal layers and compensating through the memory buffer mechanism, the system maintains hardware efficiency while improving block-error rate performance, as non-orthogonal layers can provide better error correction properties.
3Measurement precision
If VN soft information is updated in real-time during decoding, then decoding accuracy is maintained, but hardware utilization decreases due to sequential processing
Solution Approach 1:
The patent segments the decoding process into distinct stages: a first stage for computing check node messages and a second stage for updating variable node soft information. This segmentation allows each stage to be executed independently and in parallel, improving hardware utilization while maintaining decoding accuracy through the use of buffered intermediate results.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping the execution of memory access and computation operations. While the first stage computes check node messages, the second stage can simultaneously update variable node soft information using previously computed and buffered messages, keeping hardware resources continuously utilized without idle sequential transitions.
Data Source
AI summary
According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques. This may be achieved by keeping the memory access and processing hardware units active simultaneously to avoid excess decoding latency. More specifically, certain embodiments may carry out memory access and computation process simultaneously, without any effort to make the row layers mutually orthogonal to each other. Another technical advantage may be that the proposed decoding algorithm adjusts the LLRs to partially account for deviations from the layered decoding due to non-orthogonal rows.