Finite-Precision LDPC Decoding for Trapping Set Error Floors

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Solution Overview

Problem

Existing LDPC code decoders, particularly those using floating-point BP algorithms, are suboptimal for finite-length graphs, leading to performance degradation in the error floor region due to trapping sets, and quantized decoders face hardware implementation complexities and performance losses compared to floating-point BP decoders.

Innovation Solution

The development of multilevel decoders that use finite precision to represent messages, specifically designed to reduce failure rates on potential trapping sets by employing combinatorial objects as subgraphs, simplifying hardware implementation without compromising performance, and utilizing 3-bit decoders for column-weight three LDPC codes as examples.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If floating-point BP decoder is used, then decoding accuracy is improved, but hardware complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidhardware complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter of message representation from floating-point to quantized levels. The check node messages are quantized to L levels, and variable node messages are quantized to M levels, where L and M are integers. This parameter change reduces hardware complexity while maintaining decoding accuracy through carefully designed quantization schemes that preserve essential information.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent creates simplified copies of the floating-point BP decoder by using quantized message passing. Instead of implementing the full floating-point arithmetic, the patent uses lookup tables and simplified arithmetic operations that copy the essential functionality of the original decoder with reduced hardware requirements.

Inventive Principle:
Principle #26Copying

2Device complexity

If quantized decoder is used, then hardware complexity is reduced, but performance degradation occurs

Engineering Contradiction:
Improvehardware complexityVSAvoiddecoding performance
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent optimizes the quantization parameters (number of levels L and M, threshold values) to minimize performance degradation. By carefully selecting these parameters based on channel characteristics and code properties, the patent achieves near-floating-point performance with significantly reduced hardware complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces adaptive quantization where the number of levels and threshold values can be adjusted dynamically based on channel conditions and iteration number. This dynamic adaptation allows the quantized decoder to maintain high performance across varying operating conditions while keeping hardware complexity low.

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If standard BP decoding is applied to finite-length graphs, then implementation simplicity is improved, but error floor performance worsens

Engineering Contradiction:
Improveimplementation simplicityVSAvoiderror floor performance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent modifies the BP decoding parameters by introducing quantized message levels and adaptive thresholds that are specifically optimized for finite-length codes. These parameter modifications help the decoder overcome trapping sets and near-codewords that cause error floors in standard BP decoding.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent incorporates feedback mechanisms where decoding performance is monitored and used to adjust quantization parameters and thresholds. This feedback allows the system to adapt to finite-length effects and trapping sets, improving error floor performance while maintaining implementation simplicity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8458556B2Low complexity finite precision decoders and apparatus for LDPC codes
Publication Date: 2013.06.04 STMICROELECTRONICS FRANCE
  • US8458556B2 patent drawing
  • US8458556B2 patent drawing
  • US8458556B2 patent drawing

AI summary

In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region. The description and apparatus of 3-bit decoders for column-weight three LDPC codes is also presented.