LDPC Soft Decoding Tuned to Memory Failure Modes

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Solution Overview

Problem

Existing soft bit decoding schemes for memory devices do not account for the dynamic nature of failure modes, leading to suboptimal performance and increased processing burden and latency.

Innovation Solution

A machine learning model is trained to identify optimal soft bit read parameters for LDPC decoding based on hard bit read positions derived from memory devices under different failure modes, allowing for dynamic adaptation of decoding parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fixed values are used for soft bit read positions and log likelihood ratios in soft bit decoding, then processing burden and latency are reduced, but soft decoding performance degrades due to inability to account for dynamic failure modes

Engineering Contradiction:
Improvesoft decoding performanceVSAvoidprocessing burden
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic selection of soft bit read positions and log likelihood ratio values based on detected failure modes. Instead of using fixed values, the system adapts parameters in real-time according to the specific failure mode identified through hard bit decoding analysis, thereby optimizing decoding performance for each operational condition.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes key decoding parameters (soft bit read positions and log likelihood ratio values) based on the detected failure mode. Multiple sets of parameters are pre-computed for different failure modes, and the appropriate set is selected dynamically, allowing the decoder to optimize performance for each specific failure scenario.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If fixed values are used for soft bit read positions and log likelihood ratios, then device complexity is reduced, but latency increases due to suboptimal performance requiring additional processing

Engineering Contradiction:
Improvesystem throughputVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Multiple sets of soft bit read positions and log likelihood ratio values are pre-computed and stored for different failure modes before actual decoding operations. This preliminary preparation allows the system to quickly select the appropriate parameter set based on detected failure modes without performing complex real-time calculations, thereby reducing latency while maintaining high throughput.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If dynamic adaptation of decoding parameters is implemented, then error correction performance is improved, but processing complexity increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the decoding process into distinct stages: hard bit decoding to identify failure modes, failure mode classification, and selective application of pre-computed parameter sets. This segmentation allows dynamic adaptation without requiring complex real-time optimization, as each stage handles a specific aspect of the problem independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing complex real-time optimization, the system creates multiple copies of parameter sets (soft bit read positions and log likelihood ratios) for different failure modes. The appropriate copy is selected based on detected conditions, avoiding the need for complex computational processes while achieving adaptive optimization.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20260039314A1Failure mode-adaptive low-density parity check soft decoding
Publication Date: 2026.02.05 MICRON TECHNOLOGY INC
  • US20260039314A1 patent drawing
  • US20260039314A1 patent drawing
  • US20260039314A1 patent drawing

AI summary

In some implementations, a device may receive a data signal from a memory device. The device may perform a low-density parity check (LDPC) hard bit decoding on the data signal to identify a plurality of hard bit read positions (HBRPs). The device may identify, with a machine learning model using the plurality of HBRPs, a failure mode of the memory device. The device may identify a set of parameters for an LDPC soft bit decoding based on the failure mode. The device may perform the LDPC soft bit decoding on the data signal using the set of parameters.