LDPC Codeword Decoding Using Higher-Order Error Information
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Solution Overview
Problem
Conventional bit-flipping (BF) decoders in error-correction systems, such as LDPC decoding, face a 'trapping' issue where the energy of a variable node does not change across decoding iterations, preventing further bit flipping decisions and leading to decoding failures at high error floors, especially when lower order information is limited to directly connected check nodes.
Innovation Solution
The proposed solution involves using higher order information by considering the energy of variable nodes indirectly connected via satisfied and unsatisfied check nodes, computing a total energy that includes contributions from nodes at least two edges away, to make informed bit flipping decisions, thereby avoiding the trapping issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional bit-flipping decoder uses only lower order information (directly connected check nodes) for decoding, then decoding latency is reduced, but error-correction capability deteriorates due to trapping issue at high error floors
Solution Approach 1:
The patent extends the decoding information from first-order (directly connected check nodes) to higher-order (indirectly connected check nodes through intermediate variable nodes) dimensions. This dimensional expansion allows the decoder to access additional energy information that resolves trapping issues without significantly increasing latency, as the higher-order information can be computed using the existing iterative decoding framework.
Solution Approach 2:
The patent pre-computes and stores energy values for variable nodes during the iterative decoding process before making bit-flipping decisions. By having this energy information prepared in advance from both lower-order and higher-order check nodes, the decoder can make more informed decisions without adding significant computational overhead during the critical decision-making phase.
2Reliability
If deeper decoding layers with higher correction capability (e.g., MS decoder) are added to handle decoding failures, then error-correction capability is improved, but decoding latency increases
Solution Approach 1:
The patent applies higher-order information computation selectively - not all variable nodes require higher-order energy calculation. By identifying which variable nodes are in trapping states and applying higher-order information only to those cases, the system achieves improved error-correction capability without the full computational overhead of universal higher-order processing, thus minimizing latency impact.
3Reliability
If more decoding iterations are performed to resolve trapping issues, then error-correction capability is improved, but loss of time increases
Solution Approach 1:
The patent implements a feedback mechanism where the decoder monitors the energy values of variable nodes across iterations. When a variable node's energy stops changing or changes minimally (indicating a trapping state), the system activates higher-order information computation to provide corrective feedback. This targeted feedback approach resolves trapping issues without requiring extensive additional iterations, thereby reducing time loss.
Data Source
AI summary
Techniques related to improving the decoding performance of codewords, such as LDPC codewords, are described. In an example, the error-correction capability of a decoding layer is improved, where the improvements may include lowering the error floor. To do so, higher order information is used in the decoding. Higher order information refers to, during the decoding of a variable node that is in error, using information that is not limited to the variable node and check nodes connected thereto, but includes information related to variable nodes that are also in error and connected to the variable node via satisfied check nodes and related to unsatisfied check nodes connected to such variable nodes.