LDPC Layered Decoding Memory Layout to Prevent Collisions
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Solution Overview
Problem
Existing LDPC code decoding methods require significant memory capacity and are prone to memory collisions during layered decoding, which increases decoding delay and memory requirements.
Innovation Solution
The method involves determining specific input and output orders for the parity-check matrix to prevent overlapping in the column direction, allowing for efficient grouping and processing of LDPC codes using a layered decoding algorithm, which reduces memory collisions and decoding delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If layered decoding is performed using conventional memory access patterns, then decoding can proceed in parallel layers, but memory collisions occur increasing memory requirements and decoding delay
Solution Approach 1:
The parity-check matrix is divided into multiple blocks, and memory access is segmented into distinct input and output phases. Variable nodes are divided into groups that access different memory locations, preventing overlap between simultaneous read and write operations. This segmentation allows parallel layered decoding while avoiding memory collisions.
Solution Approach 2:
The patent introduces a new dimension to memory addressing by using block-based indexing and phase-based access patterns. Instead of linear memory access, the system uses two-dimensional memory organization with separate input and output memory spaces, allowing parallel operations without collision by accessing different memory dimensions simultaneously.
2Reliability
If memory capacity is increased to avoid collisions, then decoding reliability improves, but hardware complexity and cost increase
Solution Approach 1:
The patent merges the input and output memory operations into a unified memory structure with intelligent address management. By using block-based indexing and phase-separated access patterns, the system combines read and write operations in the same memory space without requiring duplicate memory banks, reducing hardware complexity while maintaining reliability.
Solution Approach 2:
The patent introduces block index registers and address calculation units as intermediaries between the decoding logic and memory. These intermediaries manage memory access patterns, ensuring that input and output operations target different memory locations without requiring additional memory capacity, thus reducing hardware complexity while maintaining decoding reliability.
3Quantity of substance
If memory access patterns are optimized to prevent collisions, then memory efficiency improves, but decoding algorithm complexity increases
Solution Approach 1:
The patent employs periodic memory access patterns where input and output operations alternate in a regular cycle. Each block processing phase follows a predetermined sequence of read and write operations with fixed periodicity, making the access pattern predictable and manageable. This periodic structure optimizes memory efficiency while keeping the control logic relatively simple through repetition rather than complex conditional branching.
4Speed
If block-based processing is used to reduce memory collisions, then decoding convergence speed improves, but the number of iterations may increase
Solution Approach 1:
The patent performs preliminary organization of the parity-check matrix into blocks with specific structural properties before decoding begins. Blocks are arranged and indexed in advance to optimize the flow of information during layered decoding. This preliminary structuring enables faster convergence by ensuring that each decoding layer has optimal access to the necessary data, reducing the total number of iterations required.
Data Source
AI summary
A channel decoding apparatus and method in a communication system using Low-Density Parity-Check (LDPC) codes are provided in which an encoded signal is received from a transmitter and decoded using a parity-check matrix. At least one of input orders and output orders of the parity-check matrix are determined so that same values are not overlapped in a column direction between the at least one of the input orders and the output orders.