Multi-Core LDPC Decoding with Scheduled Inter-Core Message Passing
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Solution Overview
Problem
Current LDPC decoding processes in wireless communication networks, particularly on GPUs and TPUs, face performance bottlenecks due to inefficient data transfer and cache usage, leading to suboptimal performance when handling large check node degrees and extensive bus system utilization.
Innovation Solution
Implementing a method where a network node distributes demodulated signal inputs across multiple processing cores and performs message passing iterations according to a set schedule, minimizing bus usage while maximizing computations within processing cores, using a bus system to update messages only at specific intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If classic message passing procedures are used for LDPC decoding on GPUs and TPUs, then decoding can be performed using standard algorithms, but performance bottlenecks occur due to inefficient data transfer and excessive bus system utilization
Solution Approach 1:
The patent divides the LDPC decoding process into distinct phases: inner iterations performed locally on each processing core without bus communication, and outer iterations that synchronize between cores. This segmentation allows computation to proceed in parallel on multiple cores with minimal bus interference, resolving the contradiction between maintaining reliable decoding and improving decoding speed.
Solution Approach 2:
The patent implements periodic bus usage where message passing between processing cores occurs only at specified outer iteration intervals rather than continuously. This periodic synchronization reduces bus system utilization and data transfer overhead while maintaining decoding reliability, directly addressing the performance bottleneck caused by excessive bus usage in classic procedures.
2Measurement precision
If full message passing iterations are performed between processing cores, then decoding accuracy is maintained, but bus latency and data transfer time increase
Solution Approach 1:
The patent extracts the essential synchronization requirement from continuous message passing, performing bus communication only at critical outer iteration points rather than at every inner iteration. This extraction maintains the necessary information exchange for decoding accuracy while eliminating unnecessary bus transfers that cause latency and time loss.
3Productivity
If data is distributed across multiple processing cores, then computational capacity is increased, but coordination overhead and bus system utilization increase
Solution Approach 1:
The patent segments the iterative decoding process into inner iterations (local computation on each core) and outer iterations (coordination between cores). This segmentation maximizes parallel computational capacity while minimizing coordination overhead by restricting inter-core communication to only the necessary outer iteration synchronization points.
Data Source
AI summary
Embodiments herein relate to a method performed by a network node for handling a received signal in a communication network. The network node distributes a first number of inputs of a demodulated signal to a first processing core of at least two processing cores and a second number of inputs of the demodulated signal to a second processing core of the at least two processing cores. The network node further decodes the first number of inputs of the demodulated signal by a first message passing within the first processing core, and decodes the second number of inputs of the demodulated signal by a second message passing within the second processing core. The network node further decodes the demodulated signal by performing a third message passing between the different processing cores over a bus that is performed according to a set schedule.