LDPC Decoding Scheduling for Lower-Complexity 5G Error Correction
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Solution Overview
Problem
The high decoding complexity of low-density parity-check (LDPC) codes in wireless networks, particularly in 5G, necessitates efficient acceleration methods to reduce cost and improve power efficiency, which is expected to be further challenged in the higher data rates of 6G networks.
Innovation Solution
The proposed solution involves scheduling the processing of LDPC base graph rows based on state transition metrics, such as parity check errors and log-likelihood ratios, to transition between different scheduling states, optimizing the processing sequence to reduce overall decoding complexity and improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC decoding is applied to ensure error correction and high spectral efficiency, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies dynamics by making the processing schedule adaptive rather than fixed. The scheduling state transitions dynamically based on parity check error metrics, allowing the decoder to adjust its behavior in real-time according to the actual decoding progress and channel conditions, thereby reducing overall complexity while maintaining reliability
Solution Approach 2:
The patent changes parameters by transitioning between different scheduling states (EO, EC, ECC, CO) based on parity check error thresholds. Each state corresponds to a different processing configuration, and the system dynamically adjusts which state to use based on the current decoding performance metrics, optimizing the balance between reliability and complexity
2Productivity
If fixed or programmable accelerators are used to reduce decoding complexity, then productivity is improved, but use of energy increases
Solution Approach 1:
The patent applies partial action by selectively processing only the necessary portions of the LDPC base graph based on the current scheduling state. Instead of always performing complete processing, the system adjusts the scope of processing to match the actual needs, reducing energy consumption while maintaining decoding productivity through adaptive scheduling
Solution Approach 2:
The patent makes the processing approach dynamic by transitioning between different scheduling states based on real-time performance metrics. This allows the system to adapt its processing intensity and method to match actual channel conditions and decoding progress, optimizing the trade-off between productivity and energy usage
3Reliability
If complete processing of all base graph rows is performed, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent applies dynamics by making the processing schedule adaptive rather than fixed. The scheduling state transitions dynamically based on parity check error metrics, allowing the decoder to adjust its behavior in real-time according to the actual decoding progress and channel conditions, thereby reducing overall complexity while maintaining reliability
Solution Approach 2:
The patent applies skipping by allowing early termination of the decoding process when certain conditions are met. By transitioning to states that process only core rows or terminate early when performance targets are achieved, the system skips unnecessary processing steps, reducing decoding time while maintaining adequate reliability through adaptive scheduling decisions
Data Source
AI summary
Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.