LDPC Deinterleaving for Robust 1024-QAM Signal Reception

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Solution Overview

Problem

There is a need for improved methods to support robust encoding, decoding, and receiving performance in digital broadcasting services, particularly for higher quality digital televisions and portable multimedia players, which existing technologies have not adequately addressed.

Innovation Solution

A transmitting apparatus and method that uses Low Density Parity Check (LDPC) coding, including an encoder to generate LDPC codewords, an interleaver to rearrange bit groups, and a modulator to map these codewords onto modulation symbols, specifically employing a parity interleaver, group interleaver, and block interleaver to enhance decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional encoding and modulation methods are used, then device complexity is reduced, but decoding and receiving performance deteriorates

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interleaver is divided into three distinct modules: a parity interleaver that processes parity bits, a group interleaver that rearranges bit groups, and a block interleaver that performs final interleaving. This segmentation allows each module to perform a specific function, improving overall decoding performance while managing complexity through functional decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The parity interleaver performs preliminary interleaving of parity bits before the group interleaver processes the entire codeword. This preliminary action ensures that parity bits are properly distributed before further processing, enhancing error correction capability without requiring complete reprocessing of all bits in each stage.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If bit groups are rearranged through multiple interleaving stages, then receiving robustness is improved, but processing time increases

Engineering Contradiction:
Improvereceiving robustnessVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The three-stage interleaving process segments the processing into parallelizable tasks. The parity interleaver, group interleaver, and block interleaver can process different portions of the data simultaneously or in an optimized sequence, reducing overall processing time while maintaining receiving robustness through comprehensive bit group rearrangement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By performing parity interleaving as a preliminary action before group interleaving, the system prepares critical parity information early in the process. This allows subsequent decoding operations to benefit from pre-organized parity bits, potentially reducing the time required for error correction during reception.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If LDPC coding with multiple interleaving modules is implemented, then encoding and decoding performance is enhanced, but device complexity increases

Engineering Contradiction:
Improveencoding and decoding performanceVSAvoidinterleaver structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interleaver is segmented into three functional modules, each handling a specific aspect of the interleaving process. This segmentation improves encoding and decoding performance by ensuring thorough bit group rearrangement while managing device complexity through modular design, where each module can be independently optimized and implemented.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The parity interleaver performs preliminary processing of parity bits before they enter the main group interleaving stage. This preliminary action enhances the overall encoding and decoding performance by ensuring parity information is properly distributed, while the modular structure keeps device complexity manageable through functional separation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11700018B2Method and apparatus for signal receiving and deinterleaving
Publication Date: 2023.07.11 SAMSUNG ELECTRONICS CO LTD
  • US11700018B2 patent drawing
  • US11700018B2 patent drawing
  • US11700018B2 patent drawing

AI summary

A signal receiving method include: demodulating a signal received from a transmitting apparatus to generate values based on 1024-quadrature amplitude modulation (QAM); splitting the values into a plurality of groups; deinterleaving the plurality of groups based on a preset interleaving order; and decoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 64800, wherein the plurality of groups are deinterleaved based on a predetermined equation.