LDPC Deinterleaving Block Layout for Lower Switching Complexity
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Solution Overview
Problem
Existing deinterleaving systems face performance degradation and increased complexity in implementation due to high switching and routing requirements, particularly when processing data for low-density parity-check (LDPC) decoders, which can lead to inefficient use of resources and reduced error correction capabilities.
Innovation Solution
The proposed solution involves optimizing the deinterleaving process by dividing data into specific blocks based on a minimum switching unit, aligning bits accordingly, and using a deinterleaver apparatus with buffers and a decoder to reduce switching and routing, thereby improving data processing efficiency and aligning with the input data unit of the LDPC decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional deinterleaving is applied to distribute burst errors, then error correction capability is improved, but switching and routing complexity increases
Solution Approach 1:
The patent segments the deinterleaving process into multiple stages: first dividing data into first data blocks, then into second data blocks, and finally into third data blocks. This segmentation allows error distribution without requiring complex global switching, as each segment processes a subset of data independently, reducing overall switching complexity while maintaining error correction capability.
Solution Approach 2:
The patent transforms the deinterleaving operation from a traditional bit-level switching approach to a block-level dimensional transformation. By operating on data blocks rather than individual bits, and by using matrix transposition operations, the patent achieves error distribution through dimensional reorganization rather than complex routing, thereby reducing switching complexity.
2Reliability
If data is divided into fine-grained blocks for deinterleaving, then error distribution is improved, but processing overhead increases
Solution Approach 1:
The patent implements a hierarchical segmentation strategy where data is first divided into first data blocks, then each first data block is divided into second data blocks, and finally each second data block into third data blocks. This multi-level segmentation achieves fine-grained error distribution while maintaining processing efficiency by organizing operations at multiple scales rather than requiring all operations at the finest granularity simultaneously.
Solution Approach 2:
The patent performs preliminary organization of data into structured blocks before the actual deinterleaving operation. By pre-organizing data into first, second, and third data blocks with specific structures, the subsequent deinterleaving operations can proceed more efficiently with simpler routing logic, reducing processing overhead despite the fine-grained nature of the operations.
3Manufacturing precision
If complex switching is used to restore original bit sequence, then deinterleaving accuracy is improved, but resource consumption increases
Solution Approach 1:
The patent divides the deinterleaving process into sequential stages operating on different data block granularities. Each stage restores a portion of the original sequence structure, achieving cumulative accuracy without requiring a single complex switching operation. This segmented approach reduces resource consumption by distributing the restoration task across multiple simpler stages.
Solution Approach 2:
The patent achieves deinterleaving accuracy through dimensional transformation of data blocks rather than through complex bit-level switching. By using matrix operations and block transpositions, the patent restores the original sequence structure with simpler, more resource-efficient operations that operate on higher-dimensional data structures rather than individual bits.
Data Source
AI summary
A deinterleaving method and a deinterleaving system performing the same are disclosed. According to an example embodiment, a data processing method includes dividing data into first data blocks of a first number of bits, performing deinterleaving on the first data blocks, and dividing deinterleaved data into second data blocks of a second number of bits and outputting the second data blocks, wherein the first number of bits is determined based on a minimum switching unit of a deinterleaving operation and the second number of bits.