LDPC De-Interleaving with Bit-Group Mapping for Broadcast Reception

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Solution Overview

Problem

There is a need for improved methods to support high decoding and receiving performance in digital broadcasting services, particularly for high-quality digital televisions and portable multimedia devices, as existing technologies do not adequately meet the demands of modern broadcasting standards.

Innovation Solution

A transmitting apparatus and interleaving method that utilize an LDPC encoder, interleaver, and modulator to map bits from a predetermined bit group of an LDPC codeword onto modulation symbols, employing a parity check matrix and cyclic shift parameters to enhance data transmission and decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional transmission methods are used, then device complexity is reduced, but decoding and receiving performance deteriorates

Engineering Contradiction:
Improvedecoding and receiving performanceVSAvoidtransmission processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC codeword is divided into multiple bit groups, and each bit group is independently interleaved using different cyclic shift amounts. This segmentation allows the receiver to process and decode different portions of the data with optimized parameters, improving overall decoding performance while managing complexity through structured division

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different bit groups within the same codeword are assigned different cyclic shift amounts based on their specific characteristics and position. This local optimization ensures that each bit group experiences the most appropriate interleaving for its requirements, enhancing receiving performance without uniformly increasing complexity across all data

Inventive Principle:
Principle #3Local quality

2Reliability

If simple interleaving is used, then processing speed is improved, but data transmission reliability deteriorates

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidinterleaving processing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The cyclic shift amounts for different bit groups are predetermined and configured before data transmission based on channel conditions and code parameters. This preliminary configuration allows the interleaving operation to proceed efficiently without real-time complex calculations, maintaining high processing speed while ensuring reliable transmission through optimized shift patterns

Inventive Principle:
Principle #10Preliminary action

3Reliability

If uniform cyclic shift amount is used for all bit groups, then device complexity is reduced, but decoding performance deteriorates

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaving configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cyclic shift amount parameter is varied across different bit groups according to a predetermined pattern or formula. This parameter change allows the system to adapt the interleaving characteristics for each bit group, improving decoding performance through diversified error distribution while maintaining manageable complexity through systematic parameter variation rather than arbitrary configuration

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11012096B2Receiving apparatus and de-interleaving method thereof
Publication Date: 2021.05.18 SAMSUNG ELECTRONICS CO LTD
  • US11012096B2 patent drawing
  • US11012096B2 patent drawing
  • US11012096B2 patent drawing

AI summary

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.