5G NR LDPC De-Interleaving With Parallel Register Processing
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Solution Overview
Problem
Current signal processing techniques for 5G NR are inefficient due to the need for modulo operations and sequential processing, which are computationally expensive and slow, especially given the shorter slot times of 5G compared to LTE.
Innovation Solution
Implement parallel processing using vector-based methods within processor registers for de-interleaving and rate de-matching, eliminating the need for modulo operations and allowing bulk memory operations, thereby speeding up the processing of radio signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If modulo operations and sequential processing are used for de-interleaving and rate de-matching, then processing accuracy is maintained, but processing speed is slow and computational complexity is high
Solution Approach 1:
The patent replaces traditional modulo operations with bitwise operations and lookup tables. Specifically, it uses AND operations with mask values to achieve the same effect as modulo operations, and employs pre-computed lookup tables to replace complex arithmetic calculations. This substitution dramatically reduces computational complexity while maintaining processing accuracy.
Solution Approach 2:
The patent divides the processing of bit sequences into parallel segments using multiple processing units. Each processing unit handles a portion of the de-interleaving and rate de-matching operations simultaneously, transforming sequential processing into parallel processing. This segmentation approach directly addresses the speed bottleneck while distributing computational load across multiple units.
2Loss of time
If traditional sequential processing methods are used, then implementation simplicity is maintained, but processing time is excessive for 5G NR slot durations
Solution Approach 1:
The patent pre-computes and stores interleaving patterns and rate de-matching parameters in lookup tables before actual signal processing occurs. These pre-computed values are readily available during de-interleaving and rate de-matching operations, eliminating the need for real-time complex calculations and significantly reducing processing time within 5G NR slot constraints.
Solution Approach 2:
The patent implements periodic processing cycles where multiple bit sequences are processed in parallel through systematically organized processing stages. The parallel processing units operate in synchronized periodic cycles, with each cycle handling a batch of de-interleaving and rate de-matching operations, thereby maximizing processing throughput within the time constraints.
Data Source
AI summary
Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.