LDPC Decoder Disparity Preprocessing for NAND Flash Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory systems face increased bit error rates due to cell-to-cell interference and retention noise as the number of bits per cell increases, leading to read errors and requiring more powerful error correction codes that reduce storage capacity.
Innovation Solution
A media controller employing Low-Density Parity-Check (LDPC) decoders and adaptive read threshold voltage adjustment based on disparity analysis to improve error correction efficiency, allowing for soft-decision decoding and reducing unnecessary LDPC decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more bits are stored per cell by increasing voltage levels, then storage capacity increases, but bit error rate increases due to cell-to-cell interference and retention noise
Solution Approach 1:
The patent changes the parameter of read threshold voltage dynamically based on detected data patterns. By adjusting the threshold voltage parameter according to the actual disparity between expected and actual bit counts, the system adapts to varying noise conditions and maintains reliable decoding even with higher storage capacity cells
Solution Approach 2:
The patent implements a feedback mechanism where the LDPC decoder monitors the disparity between expected and actual bit counts in the received data. This feedback information is used to adjust the read threshold voltage for subsequent decoding operations, creating a closed-loop system that continuously optimizes for error correction performance
2Reliability
If more powerful error correction codes are used to reduce bit error rates, then reliability improves, but storage capacity decreases due to increased overhead
Solution Approach 1:
The patent makes the decoding process dynamic by conditionally performing LDPC decoding based on disparity detection. Instead of always applying powerful error correction, the system dynamically determines whether decoding is necessary by comparing expected versus actual bit counts, thereby reducing unnecessary overhead while maintaining reliability when needed
3Reliability
If LDPC decoding is performed on all read data, then error correction reliability improves, but power consumption increases
Solution Approach 1:
The patent applies partial action by performing LDPC decoding only on a subset of read data that exhibits disparity between expected and actual bit counts. Rather than universally applying error correction to all data, the system selectively decodes only those portions that appear problematic based on the disparity criterion, thereby reducing overall power consumption while maintaining data accuracy
Data Source
AI summary
Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device.