LDPC Code Structure and Interleaving for Burst Error Resilience
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Solution Overview
Problem
In data transmission using LDPC codes, ensuring favorable communication quality is challenging due to issues like burst errors and erasures, which degrade decoding performance and increase power consumption.
Innovation Solution
The implementation of a transmission and reception system that employs LDPC codes with a dual diagonal structure parity matrix and interleaving techniques, such as parity interleaving and block interleaving, to improve error tolerance and decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes with conventional structures are used, then decoding performance is acceptable under ideal conditions, but communication quality degrades significantly in the presence of burst errors and erasures
Solution Approach 1:
The parity check matrix is segmented into multiple blocks with a dual-diagonal structure, where each block contributes to error correction capability. The code is divided into information bits and parity bits with specific positioning that enhances resilience against burst errors by distributing error impacts across different segments of the code structure.
Solution Approach 2:
The patent applies preliminary interleaving operations on both parity and information bits before transmission. This preliminary arrangement repositions bits to distribute burst errors across multiple code words, preventing concentrated error patterns that would degrade decoding performance. The interleaving is performed in advance based on predetermined patterns.
2Ease of operation
If conventional LDPC decoding is used, then implementation is straightforward, but power consumption increases due to repeated decoding attempts
Solution Approach 1:
The patent modifies key parameters of the LDPC code structure, specifically using a dual-diagonal parity check matrix with optimized dimensions and interleaving patterns. These parameter changes improve decoding convergence characteristics, reducing the number of iterative decoding attempts needed and thereby lowering power consumption while maintaining implementation feasibility.
3Reliability
If standard LDPC codes are used, then basic error correction is provided, but tolerance to burst errors and erasures is insufficient
Solution Approach 1:
The patent creates a composite error correction structure by combining LDPC coding with interleaving techniques. The dual-diagonal parity check matrix is复合ed with specific interleaving patterns to form a hybrid structure that provides enhanced tolerance to both random errors and burst errors, as well as erasures, making the system adaptable to various channel conditions.
Data Source
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AI summary
The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 9/16 or 10/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.