LDPC ECC Allocation Across Memory Pages for Bit Error Imbalance
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Solution Overview
Problem
As memory cell density increases, maintaining the reliability of information stored in memory devices becomes challenging due to increased error proneness in data storage, particularly in multi-level cell configurations where bits are more likely to experience errors, affecting the accuracy of data retrieval and storage.
Innovation Solution
The implementation of a memory device architecture that allocates more error correction code (ECC) bits to error-prone pages based on bit position analysis, using a generator matrix for LDPC coding to generate ECC sets, and organizing data and ECC into specific pages to enhance error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased, then storage capacity is improved, but error rate increases
Solution Approach 1:
The patent applies local quality by allocating different numbers of ECC bits to different pages based on their error characteristics. Specifically, pages containing bits at positions more prone to errors (such as LSB pages in multi-level cell configurations) are allocated more ECC bits, while pages with more reliable bits are allocated fewer ECC bits. This localized differentiation of error protection resources directly addresses the increased error rate in high-density memory while optimizing overall storage efficiency.
Solution Approach 2:
The patent changes the parameter of ECC bit allocation dynamically based on page characteristics. By analyzing bit position error rates and adjusting the number of ECC bits allocated to each page accordingly, the system adapts the error correction capability to match the actual error proneness of different data regions, thereby maintaining reliability across the entire high-density memory array.
2Reliability
If more ECC bits are allocated to error-prone pages, then data reliability is improved, but memory resource utilization decreases
Solution Approach 1:
Instead of uniformly allocating ECC bits across all pages, the patent implements local quality by differentiating ECC allocation based on the specific error characteristics of each page. Pages with higher error rates receive more ECC bits, while pages with lower error rates receive fewer ECC bits. This targeted approach ensures data reliability where needed most while preserving memory resource utilization in less vulnerable areas.
Solution Approach 2:
The patent applies partial action by allocating ECC bits selectively rather than excessively to all pages. By providing enhanced error correction only to pages that actually require it (those with error-prone bit positions), the system avoids the resource waste that would result from uniform over-protection, thereby optimizing the balance between reliability and resource utilization.
Data Source
AI summary
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.