LDPC ECC Encoder Circuit With Dual-Diagonal Parity Matrix
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Solution Overview
Problem
The increasing bit errors in semiconductor devices due to shrinking fabrication design rules and the inefficiency of existing error correcting code (ECC) operations in volatile and nonvolatile memory devices, particularly in flash memory devices, necessitate an improved ECC encoding method that reduces complexity while enhancing error floor and waterfall characteristics.
Innovation Solution
An ECC encoding circuit utilizing a parity check matrix structure with a dual diagonal arrangement of sub-matrices, including block matrices B, D, and E, and a bit accumulator to generate encoded codewords with improved error correction capabilities, specifically using LDPC codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing ECC operations are used in memory devices, then error correction can be performed, but the encoding complexity is high and error floor characteristics are poor
Solution Approach 1:
The parity check matrix is divided into multiple block matrices (T, B, D, E) with specific sub-matrix arrangements. This segmentation allows the encoding process to be broken down into simpler operations on smaller matrices, reducing overall encoding complexity while maintaining good error floor characteristics through the structured distribution of parity bits.
Solution Approach 2:
The patent employs a specific parameter configuration where the parity check matrix uses a dual diagonal structure with block matrices positioned at specific locations. The sub-matrices are arranged in a pattern where block T and block E are in the same sub-column, and block B and block D are in the same sub-column, creating an optimized parameter set that improves error floor performance without increasing complexity.
2Productivity
If fabrication design rules are shrunk to increase device density, then more devices can be integrated, but bit errors increase rapidly
Solution Approach 1:
The ECC encoding is performed in advance before data is stored in the memory device. By pre-calculating and adding parity bits using the optimized parity check matrix structure, the system prepares error correction capability beforehand, allowing the memory device to tolerate higher bit error rates that inevitably occur with shrunk fabrication rules.
Solution Approach 2:
The patent converts the harmful effect of increased bit errors (caused by fabrication shrinkage) into a benefit by designing an ECC system that specifically targets and corrects these errors. The dual diagonal block matrix structure is optimized to handle the specific error patterns that emerge from advanced fabrication processes, turning the problem of higher error rates into an opportunity to demonstrate improved error correction capability.
3Reliability
If a complex parity check matrix structure is used to improve error correction, then error floor characteristics improve, but encoding complexity increases
Solution Approach 1:
The parity check matrix uses an asymmetric dual diagonal structure where block matrices are positioned non-uniformly. Block T and block E are placed in one sub-column while block B and block D are placed in another sub-column, creating an asymmetric pattern that optimizes error correction performance. This asymmetric arrangement improves waterfall characteristics by creating favorable error propagation patterns without requiring a fully dense complex matrix.
Solution Approach 2:
The complex parity check matrix is segmented into four main block matrices (T, B, D, E), each containing sub-matrices. This segmentation transforms a single complex matrix operation into multiple simpler block matrix operations, reducing the computational burden while maintaining the structural complexity needed for good waterfall characteristics.
Data Source
AI summary
A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.