LDPC ECC Switching Using Failure Probability in NAND Controllers
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Solution Overview
Problem
NAND flash controllers face challenges in accurately determining when to switch from weaker to stronger error correction codes (ECCs) due to the variable error correction capabilities of low density parity check (LDPC) codes, which can result in premature or delayed switching, leading to uncorrectable errors.
Innovation Solution
Implementing an error correction code selection circuit that uses reliability statistics and distribution properties of ECCs to predict uncorrectable error correction code (UECC) failure rates and switch from weaker to stronger LDPC codes before actual failures occur, utilizing an offline characterization method and look-up table to control UECC failure rates within specified limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If real-time testing of UECC failure rate is implemented to determine when to switch from weaker to stronger LDPC codes, then the accuracy of ECC switching decision is improved, but the system complexity and cost increase
Solution Approach 1:
The patent performs offline characterization of LDPC codes to pre-determine the number of errors that cause first-time UECC failures across different P/E cycles. These results are stored in a look-up table, eliminating the need for real-time testing during actual operation. The controller simply queries the pre-computed table based on current P/E cycle count and observed error counts to make switching decisions.
Solution Approach 2:
The patent creates a simplified model by copying the essential characteristics of LDPC code performance into a look-up table. Instead of implementing complex real-time testing and analysis mechanisms, the system uses a pre-computed representation of UECC failure patterns that can be quickly queried and applied during operation.
2Productivity
If switching to a stronger LDPC code is delayed to avoid premature switching, then weaker codes can be used longer reducing overhead, but the risk of uncorrectable errors increases
Solution Approach 1:
The patent implements a feedback mechanism where the controller continuously monitors the number of errors corrected by the current LDPC code and compares this against the look-up table thresholds. When the error count approaches the pre-determined UECC failure point, the system automatically triggers a switch to a stronger code, ensuring reliability while optimizing storage efficiency.
Solution Approach 2:
The patent changes the operating parameters of the ECC system by dynamically switching between different LDPC codes with varying error correction capabilities. The look-up table provides pre-calculated switching points that optimize the balance between using weaker codes for storage efficiency and stronger codes for data integrity based on the actual error conditions observed.
3Reliability
If switching from weaker to stronger LDPC codes occurs too early, then UECC failures are avoided, but storage efficiency decreases due to unnecessary use of stronger codes
Solution Approach 1:
The patent performs preliminary analysis offline to determine the exact error counts at which UECC failures occur for each LDPC code across different P/E cycles. This pre-computed knowledge is stored in the look-up table, enabling the controller to switch codes at the precise optimal moment - just before UECC failures would occur - thereby avoiding both premature and delayed switching.
Solution Approach 2:
The patent implements a dynamic ECC switching strategy where the optimal switching point is not fixed but adapts based on the actual error conditions and P/E cycle count. The look-up table provides dynamic thresholds that reflect the actual performance characteristics of LDPC codes under different aging conditions, enabling optimal switching decisions that balance reliability and storage efficiency.
Data Source
AI summary
An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes.