LDPC Decoder Edge Memory Indexing to Reduce Memory Footprint
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Solution Overview
Problem
Traditional LDPC decoder designs require significant memory and processing resources due to the large footprint of edge memory, which stores extrinsic information for each edge, necessitating a reduction in size while maintaining performance.
Innovation Solution
The edge memory is reformatted into a value memory and an index memory, where the value memory stores possible extrinsic information values for check nodes, and the index memory stores indices identifying the applicable values for each edge, reducing the overall size of the edge memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional edge memory architecture stores extrinsic information for every edge, then decoding performance is maintained, but memory footprint becomes very substantial
Solution Approach 1:
The patent segments the traditional edge memory into two separate components: a value memory that stores extrinsic information values shared by multiple edges, and an index memory that stores indices mapping edges to their corresponding values. This segmentation allows the system to maintain decoding performance while significantly reducing the total memory footprint by eliminating redundant storage of identical extrinsic information values across multiple edges.
2Use of energy by stationary object
If edge memory size is reduced through reformating, then cost and power consumption decrease, but memory architecture complexity increases
Solution Approach 1:
The patent uses copying by storing extrinsic information values in a shared value memory and referencing them through indices in the index memory. Instead of copying full extrinsic information for each edge, the system copies only small index values that point to the actual data in the value memory. This approach reduces power consumption while managing architecture complexity through efficient reference-based access patterns.
Data Source
AI summary
Systems, devices, and methods are disclosed for a novel edge memory architecture. An architecture is described wherein the extrinsic information typically stored inside the edge memory is reformatted. Instead of storing the extrinsic information for every edge, the novel edge memory stores a set of possible extrinsic information values for a check node in a “value memory.” The edge memory also stores an index for each edge in a second, “index memory,” identifying which value stored in the value memory applies to each respective edge.