LDPC Encoder Block Segmentation for Long Codeword Parallelism

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Solution Overview

Problem

The encoding complexity of Spatially Coupled Irregular Repeat Accumulate (SC-IRA) codes increases linearly with the length of the codeword, making it challenging to process long codewords efficiently.

Innovation Solution

An encoding apparatus and method that utilize a parity check matrix with multiple blocks, including a first and second information sub-matrix and parity sub-matrix, where the bit determiner and bit modifier adjust sub-parity bits to reduce encoding complexity by reversing bit values based on the last sub-parity bit, allowing for parallel encoding operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the codeword length is increased to improve LDPC code performance, then the encoding complexity increases linearly

Engineering Contradiction:
ImproveLDPC code performanceVSAvoidencoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity check matrix is divided into multiple blocks, where each block contains information sub-matrices and parity sub-matrices. This segmentation allows the encoding process to be divided into independent parallel operations for each block, reducing the linear encoding complexity while maintaining long codeword length for improved LDPC performance.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the codeword length is increased to support parallel decoding at the decoder, then the encoding complexity increases

Engineering Contradiction:
Improveparallel decoding capabilityVSAvoidencoding complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The encoding apparatus divides the parity check matrix into multiple blocks that can be processed independently. Each block contains information sub-matrices and parity sub-matrices that can be encoded in parallel, enabling both parallel encoding and parallel decoding operations without increasing overall complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a block structure dimension to the parity check matrix, organizing it as a two-dimensional array of blocks rather than a single large matrix. This dimensional change enables parallel processing across blocks while maintaining the long codeword length needed for decoder parallelization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If the SC-IRA code is used to reduce encoding complexity, then the encoding complexity still increases linearly with codeword length

Engineering Contradiction:
Improveencoding complexityVSAvoidencoding speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The SC-IRA encoding process is segmented into multiple independent block operations. Each block can be encoded simultaneously without waiting for previous blocks, transforming the linear complexity into constant-time parallel operations and significantly improving encoding speed.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9660669B2Encoding apparatus and encoding method thereof
Publication Date: 2017.05.23 SAMSUNG ELECTRONICS CO LTD
  • US9660669B2 patent drawing
  • US9660669B2 patent drawing
  • US9660669B2 patent drawing

AI summary

An encoding apparatus which performs encoding such as Low Density Parity Check (LDPC) encoding is provided. The encoding apparatus includes: an encoder encoding input bits using a parity check matrix including a plurality of blocks, each being formed of a first information word sub-matrix and a first parity sub-matrix arranged next to each other, and a second information sub-matrix and a second parity sub-matrix arranged next to each other; a bit determiner determining a value of a last sub-parity bit among sub-parity bits generated by encoding the input bits with respect to a first block among the plurality of blocks; and a bit modifier reversing values of bits generated by encoding the input bits with respect to a second block next to the first block based on the value of the last parity bit among the sub-parity bits generated by the encoding with respect to the first block.