Programmable LDPC Encoder Using Speculative Parity Recursion
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Solution Overview
Problem
Low-density parity check (LDPC) codes face challenges in implementing low error floors without increasing code block length, which can require significant memory and computational resources, limiting their flexibility.
Innovation Solution
The development of programmable LDPC encoders that utilize various inversion mechanisms, such as recursive computation, speculative recursion, and blockwise inversion, to efficiently generate parity symbols for LDPC codes with different parity check matrix structures, allowing for flexible operation and reduced resource requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes use larger code block length to achieve low error floors, then error floor performance is improved, but memory requirements and computational power increase
Solution Approach 1:
The parity check matrix H is divided into sub-matrices (H1, H2, H3, H4) that can be processed independently. The encoding process is segmented into multiple stages where intermediate results are computed and stored in smaller buffers rather than requiring full-code-length buffers. This segmentation allows achieving low error floor performance through proper matrix structure design without proportionally increasing memory requirements.
Solution Approach 2:
The patent transforms the traditional time-domain sequential processing into a spatial-domain parallel processing architecture. By organizing the computation across multiple processing units that operate simultaneously on different portions of the code, the system achieves high reliability with reduced memory requirements at any given moment, as memory is reused across different computational stages.
2Reliability
If LDPC codes use larger code block length to achieve low error floors, then error floor performance is improved, but computational power requirements increase
Solution Approach 1:
The computational process is divided into segments corresponding to the sub-matrix structure of H. Each processing unit computes a portion of the parity symbols using its assigned sub-matrix, reducing the computational burden on any single unit. The overall computational complexity is distributed across multiple units operating in parallel, achieving low error floor performance without concentrating excessive computational power requirements in one location.
Solution Approach 2:
The system employs a dynamic architecture where processing units can be selectively activated based on the specific LDPC code configuration being used. The computational resources are dynamically allocated to match the actual requirements of the code block, allowing the system to achieve low error floor performance when needed while consuming minimal computational power for simpler encoding tasks.
3Productivity
If LDPC encoders are designed for specific code structures, then encoding efficiency is improved, but flexibility decreases
Solution Approach 1:
The encoder architecture is designed as a universal platform that can handle multiple LDPC code structures through configurable parameters. The same physical hardware structure can be programmed to implement different parity check matrix configurations by reconfiguring the connections and computation paths. This multi-functionality allows the encoder to maintain high efficiency for each specific code type while being adaptable to various code structures.
Solution Approach 2:
The encoder employs dynamic reconfiguration capabilities that allow it to adapt its internal structure based on the specific LDPC code being encoded. Processing units can be dynamically connected to different memory buffers and computation paths depending on the code configuration. This dynamic adaptability enables the system to optimize encoding efficiency for each specific code structure while maintaining flexibility across different code types.
Data Source
AI summary
Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.