Quasi-Cyclic LDPC Encoder Layout for Co-Channel Robust Reception
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Solution Overview
Problem
Current terrestrial TV broadcasting systems face co-channel interference issues, leading to white spaces where frequency reuse is not possible, resulting in deteriorated spectrum efficiency, and existing LDPC codes are not optimized for the DVB broadcast standard or specific LDPC encoding methods.
Innovation Solution
A new LDPC code with a length of 64800 and code rate of 3/15 is developed, utilizing a quasi-cyclic LDPC encoding technique with a specific sequence and structure, including a systematic part, first parity part, and second parity part, to efficiently encode and decode signals, reducing memory requirements and improving decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a new LDPC code with length 64800 and code rate 3/15 is developed using quasi-cyclic encoding technique, then spectrum efficiency is improved and white spaces are eliminated, but device complexity and memory requirements increase
Solution Approach 1:
The LDPC codeword is segmented into three distinct parts: systematic part (12960 bits), first parity part (1800 bits), and second parity part (50040 bits). The parity check matrix is also segmented into blocks that can be processed separately. This segmentation allows the encoder to handle different parts of the code with appropriate processing methods, improving reception robustness while managing device complexity through modular design.
Solution Approach 2:
The patent employs quasi-cyclic LDPC encoding with specific parameter configurations: code length N=64800, code rate 3/15, and circulant permutation matrix size of 360×360. By optimizing these parameters and using a specific sequence structure with 41 rows, the encoding achieves improved spectrum efficiency and elimination of white spaces while keeping the memory requirements manageable through the quasi-cyclic structure.
2Quantity of substance
If accumulation is performed at parity bit addresses updated using a sequence with 41 rows, then memory requirements are reduced, but encoding time and processing complexity increase
Solution Approach 1:
The sequence with 41 rows is pre-configured and stored in memory before the actual encoding process. The sequence defines the parity bit addresses in advance, allowing the encoder to quickly access and update addresses during encoding without real-time calculation. This preliminary preparation reduces the memory size required during encoding while the structured sequence minimizes processing time through efficient address updates.
Solution Approach 2:
The quasi-cyclic structure uses repeated patterns of circulant permutation matrices throughout the parity check matrix. Instead of storing the entire 64800×2160 matrix, the encoder stores smaller 360×360 circulant blocks and uses copying/repetition to generate the full matrix structure. This reduces memory requirements significantly while the regular structure allows efficient processing.
Data Source
AI summary
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).