LDPC Encoder Structure for Co-Channel Robust TV Broadcasting
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Solution Overview
Problem
Current terrestrial TV broadcasting systems face significant co-channel interference issues, leading to white spaces where frequency reuse is not possible, resulting in deteriorated spectrum efficiency, especially in areas where timing and frequency synchronization between signals are not guaranteed.
Innovation Solution
A new Low Density Parity Check (LDPC) code with a length of 16200 and a code rate of 5/15 is developed, utilizing a specific LDPC encoding technique that includes a systematic part, a first parity part, and a second parity part, along with a sequence for efficient encoding and decoding, allowing for robust reception and demodulation of terrestrial cloud broadcast signals in overlapping areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If terrestrial TV broadcasting uses current frequency allocation, then broadcasting coverage is achieved, but co-channel interference occurs and white spaces are created reducing spectrum efficiency
Solution Approach 1:
The patent applies parameter changes by implementing LDPC encoding with specific code rates (1/2, 2/3, 3/4) and code lengths (16200, 6480, 1800) to transform the broadcasting system's error correction capability. This allows the system to maintain reliable reception in co-channel interference environments while enabling frequency reuse, thereby improving spectrum efficiency without sacrificing reception robustness
Solution Approach 2:
The patent implements feedback mechanisms through iterative decoding processes and signal quality monitoring that allow the receiver to adapt to interference conditions. The system uses feedback from decoding performance to adjust equalization and demodulation parameters, enabling robust reception in overlapping signal areas while maintaining spectrum efficiency
2Productivity
If frequency reuse is implemented in overlapping areas, then spectrum efficiency improves, but co-channel interference makes signal demodulation difficult without guaranteed timing and frequency synchronization
Solution Approach 1:
The patent applies preliminary action by performing LDPC encoding at the transmitter with predefined parity check matrices and accumulation structures. This pre-processing of the signal with robust error correction codes enables the receiver to reliably demodulate signals even without perfect timing and frequency synchronization, thus allowing frequency reuse to improve spectrum efficiency while maintaining demodulation reliability
Solution Approach 2:
The system changes parameters by using different code rates and code lengths based on channel conditions and service requirements. This flexibility allows optimization of the balance between spectrum efficiency and demodulation reliability for different broadcasting scenarios, enabling successful frequency reuse
3Reliability
If LDPC encoding with code length of 16200 and code rate of 5/15 is implemented, then reception robustness improves, but encoding complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the LDPC encoding process into systematic parts and parity parts, with the codeword structured as information bits followed by parity bits. The parity check matrix is segmented into accumulation structures that can be processed in stages, reducing the computational burden while maintaining the robustness benefits of the 5/15 code rate
Solution Approach 2:
The system manages complexity by offering multiple code rate options (1/2, 2/3, 3/4, 5/15) and code length options (16200, 6480, 1800). This allows the receiver to select appropriate parameters based on channel conditions and processing capabilities, achieving reception robustness when needed while reducing encoding complexity in less challenging scenarios
Data Source
AI summary
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).