LDPC Decoder Erasure Patterns for Storage Device Manufacturing Tests
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Solution Overview
Problem
Current testing techniques for low-density parity-check (LDPC) codes in storage devices are inadequate in determining optimal testing parameters, leading to either overly optimistic or pessimistic manufacturing yields, as the error rate functions lack sufficient resolution to balance between passing and failing devices, and do not adequately account for field-grown defects.
Innovation Solution
Implementing a manufacturing test system that uses LDPC iterations and error rate functions to determine testing parameters, including the number of LDPC iterations (Ntesting) and passing error rates, while applying erasure patterns to LDPC decoders to generate error rate functions with increased resolution, allowing for more combinations of iterations and sector failure rates to select suitable testing parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing techniques are used with standard error rate functions, then the testing process is simple and quick, but the manufacturing yield determination is inaccurate due to insufficient resolution
Solution Approach 1:
The patent segments the error rate function evaluation by introducing multiple erasure patterns (e.g., different numbers and positions of erasures) to create multiple distinct error rate curves. Each curve provides resolution at different error rate points, collectively achieving high overall resolution without requiring an excessively complex testing system
Solution Approach 2:
The patent changes testing parameters by varying the number of LDPC iterations (Ntesting) and applying different erasure patterns to generate error rate functions with increased resolution. This allows selective optimization of testing precision for different device types or defect scenarios without universally increasing system complexity
2Measurement precision
If the number of LDPC iterations (Ntesting) is increased to improve testing accuracy, then the error rate measurement becomes more precise, but the testing time increases
Solution Approach 1:
The patent applies partial action by using a limited number of LDPC iterations (Ntesting) that is sufficient to achieve the required measurement precision for manufacturing yield determination, rather than using the maximum possible iterations. This is complemented by using multiple erasure patterns to achieve overall high precision without requiring each individual test to be excessively long
Solution Approach 2:
The patent performs preliminary action by generating error rate functions through multiple erasure patterns before actual device testing. These pre-generated functions are used to determine the optimal Ntesting value and passing error rate, allowing the actual testing to be performed efficiently with predetermined parameters rather than requiring extensive iterative testing
3Adaptability or versatility
If erasure patterns are applied to increase error rate function resolution, then more combinations of iterations and sector failure rates become available, but the testing procedure becomes more complex
Solution Approach 1:
The patent applies universality by designing a testing framework where multiple erasure patterns are used to serve multiple purposes: determining passing error rates, selecting optimal Ntesting values, and characterizing device performance across different error conditions. This multi-functional approach increases adaptability without proportionally increasing operational complexity
Solution Approach 2:
The patent uses copying by generating multiple error rate functions through different erasure patterns, where each function serves as a reference curve for determining testing parameters. These copied functions allow selection of optimal testing parameters without requiring complex real-time calculations during actual device testing
4Reliability
If the passing error rate threshold is set to ensure high quality standards, then fewer defective devices are passed, but the manufacturing yield decreases
Solution Approach 1:
The patent implements feedback by using the error rate functions generated through multiple erasure patterns to determine an optimized passing error rate threshold. This threshold is selected to achieve the desired balance between reliability and yield, allowing manufacturers to adjust the threshold based on the specific error rate characteristics observed in the tested device population
Solution Approach 2:
The patent enables parameter changes by allowing the passing error rate threshold and Ntesting value to be selected from multiple options based on the generated error rate functions. This allows optimization of the passing criterion to achieve the desired balance between reliability and manufacturing yield for different device types and application requirements
Data Source
AI summary
A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.