LDPC Encoding with Error Floor Prevention Bits
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Solution Overview
Problem
Low-density parity check (LDPC) codes experience performance deterioration due to the error floor phenomenon, particularly in systematic LDPC, caused by trapping sets during encoding and decoding, which existing technologies have not effectively addressed.
Innovation Solution
Inserting error floor prevention bits into specific positions of the information bit sequence, determined through simulations, to modify the LDPC encoding process, and assigning log likelihood ratio (LLR) values during decoding using the sum-product algorithm to prevent performance deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC encoding and decoding is performed using conventional methods, then encoding and decoding operations can be executed, but performance deterioration occurs due to the error floor phenomenon caused by trapping sets
Solution Approach 1:
The patent applies preliminary action by inserting error floor prevention bits into specific positions of the information bit sequence before encoding. These bits are placed at positions determined through simulations to prevent trapping set formation. During decoding, preset LLR values are assigned to these prevention bit positions before the sum-product algorithm executes, proactively preventing the error floor phenomenon rather than correcting it after occurrence
Solution Approach 2:
The patent applies local quality by treating specific positions in the bit sequence differently from others. Error floor prevention bits are inserted at predetermined positions identified through simulations as problematic areas. During decoding, only these specific positions receive preset LLR values while other positions undergo normal decoding processing, applying different quality treatment to different parts of the data
2Reliability
If error floor prevention bits are inserted into the information bit sequence, then the error floor phenomenon is prevented, but the code rate is adjusted and processing complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the information bit sequence structure through insertion of error floor prevention bits at specific positions. This changes the length and composition parameters of the bit sequence. During decoding, the LLR values for these specific positions are changed to preset values, altering the probability parameters used in the sum-product algorithm to prevent error floor
Data Source
AI summary
Disclosed are an LDPC encoding/decoding method and a device using same. The method includes the steps of: (a) generating an information bit sequence by determining information bits to be encoded from among a group of information bits; (b) generating a modified information bit sequence by inserting a preset error floor prevention bit into at least one preset position in the information bit sequence; (c) generating a parity check bit on the basis of the modified information bit sequence; and (d) performing encoding by using the modified information bit sequence and the parity check bit. According to the disclosed method, performance degradation of LDPC encoding and decoding due to an error floor phenomenon can be prevented.