Non-Binary LDPC Parity-Check Decoding With FIFO Candidate Selection
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Solution Overview
Problem
The high computational complexity of non-binary LDPC code decoding algorithms, particularly in implementing the Belief Propagation (BP) algorithm, makes it prohibitive for large values of q, limiting efficient hardware and software implementations.
Innovation Solution
A method for managing parity-check node calculations in a bipartite graph representation using FIFO memories and a calculation operation that selects the most reliable combinations from input messages, reducing the complexity by iteratively determining output messages and updating FIFO memories, thereby optimizing surface area and clock frequency in FPGA implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Belief Propagation algorithm is used for non-binary LDPC code decoding, then decoding accuracy is improved, but computational complexity becomes prohibitive for large values of q
Solution Approach 1:
The parity-check node processing is segmented into multiple stages: initialization stage (computing candidate combinations), selection stage (selecting top nm candidates), and output stage (generating final message). This segmentation allows the complex BP algorithm to be broken down into manageable steps that can be efficiently implemented in hardware, reducing overall computational complexity while maintaining decoding accuracy.
Solution Approach 2:
Instead of computing all q² possible combinations of input messages, the algorithm performs partial action by computing only the top nm candidates (where nm << q²) based on reliability metrics. This selective computation significantly reduces the number of operations from O(q²) to O(nm), making the decoder feasible for large q values while still achieving good decoding performance.
2Reliability
If the number of computed combinations in parity-check node is increased to improve message reliability, then output message accuracy is improved, but resource requirements and surface area increase
Solution Approach 1:
The algorithm computes only the necessary number of candidate combinations (top nm) rather than all possible combinations. By using a threshold-based selection approach, it achieves sufficient message reliability with a limited number of computations, thereby reducing the surface area required for hardware implementation while maintaining acceptable decoding performance.
Solution Approach 2:
The algorithm introduces the parameter nm (number of candidates to process) as a controllable variable that balances between message reliability and resource consumption. By adjusting nm, the system can optimize the trade-off between decoding accuracy and hardware surface area, allowing flexible adaptation to different application requirements.
3Measurement precision
If the decoding algorithm processes all possible symbol combinations, then decoding precision is improved, but clock frequency and processing speed decrease
Solution Approach 1:
The algorithm processes only the most promising candidate combinations (top nm based on reliability metrics) rather than exhaustively processing all q² combinations. This partial processing approach maintains sufficient decoding precision by focusing computational resources on the most likely candidates, while achieving significant speed improvements that enable real-time communication applications.
Solution Approach 2:
The algorithm performs preliminary sorting and selection of input message candidates based on their reliability metrics before the main processing stage. By pre-identifying and ranking the top nm candidates from each input message, the system prepares the data in advance, allowing the main processing stage to operate more efficiently at higher clock frequencies without sacrificing decoding precision.
Data Source
AI summary
A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a representation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.