Non-Binary LDPC Parity-Check Decoding With FIFO Reliability Lists
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Solution Overview
Problem
The high computational complexity of decoding non-binary LDPC codes, particularly in implementing algorithms like Belief Propagation, makes efficient hardware and software implementations challenging due to the prohibitive cost of processing large Galois fields.
Innovation Solution
A method and apparatus for managing a parity-check node calculation unit in a bipartite graph-based error-correcting code decoder, utilizing FIFO memories to efficiently process input messages and reduce complexity by selecting and updating output messages based on reliability, specifically using a calculation operation that prioritizes maximum reliability, thereby reducing the computational load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Belief Propagation algorithm is used for decoding non-binary LDPC codes, then decoding accuracy is improved, but computational complexity increases prohibitively
Solution Approach 1:
The patent segments the Galois field GF(q) into multiple subfields or partitions the set of q possible symbol values into groups. By processing messages in terms of these partitions rather than individual symbols, the algorithm reduces the number of operations from O(q) to O(sqrt(q)) or O(log q), significantly lowering computational complexity while preserving decoding accuracy through the maintained algebraic structure of the field.
Solution Approach 2:
The patent transforms the representation of reliability information by changing the parameter space. Instead of maintaining q separate reliability values for each symbol in GF(q), the invention uses a transformed representation with fewer parameters (e.g., using quadratic residues or partition-based metrics) that captures the essential reliability information while reducing the computational burden of message passing operations.
2Reliability
If large Galois fields are used for non-binary LDPC codes, then error correction capability is improved, but hardware implementation cost increases
Solution Approach 1:
The patent applies segmentation to the hardware architecture by dividing the large Galois field operations into smaller subfield operations or partition-based processing units. This allows the hardware to implement complex GF(q) decoding by composing simpler computational blocks, reducing the surface area and resource requirements while maintaining support for large field sizes and their associated error correction capabilities.
3Reliability
If comprehensive message processing is performed at each parity-check node, then decoding reliability is improved, but processing time increases
Solution Approach 1:
The patent implements preliminary action by pre-computing and storing lookup tables for common message passing operations, such as the check node processing functions and metric transformations. These pre-computed tables allow the decoder to perform comprehensive reliability assessments using simple table lookups rather than complex real-time calculations, significantly reducing processing time while maintaining accurate reliability evaluation.
Data Source
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AI summary
A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a representation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.