LDPC Decoder Fixed Permutation Layout for Lower Interconnect Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low-density parity-check (LDPC) decoding is computationally complex, leading to increased memory requirements and interconnection complexity, which hinders efficient processing in systems like 60 GHz millimeter wave systems.
Innovation Solution
An iterative LDPC decoding system comprising a shift-register means for storing bit estimates, a parity-check processing means for generating messages, a combining means for updating bit estimates, and a fixed permutation means for facilitating storage and access, along with a second shift-register means for storing messages and subtracting earlier messages from updated bit estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If iterative LDPC decoding is implemented using conventional message-passing algorithms, then decoding accuracy is improved, but computational complexity increases
Solution Approach 1:
The parity-check matrix H is divided into multiple sub-matrices, and the decoding process is segmented into multiple processing stages. Each stage handles a portion of the computational work, allowing the overall complex decoding task to be broken down into manageable segments that can be processed in parallel or sequentially with reduced complexity at each step.
Solution Approach 2:
The decoder employs dynamic scheduling of processing stages based on the iterative decoding progress. The computational resources are dynamically allocated across different iterations and processing stages, allowing the system to adapt the decoding process to maintain accuracy while optimizing computational efficiency at each iteration.
2Productivity
If computational complexity is reduced through simplified decoding techniques, then processing speed is improved, but memory requirements increase
Solution Approach 1:
The memory structure is segmented into multiple banks, with each bank storing a portion of the bit estimates and intermediate results. This segmentation allows the decoder to access different memory banks in parallel during different processing stages, reducing the memory access time and improving processing speed without requiring a single large memory block.
Solution Approach 2:
The memory organization transitions from a two-dimensional array structure to a three-dimensional bank-based structure. This dimensional change allows the memory system to accommodate the reduced-complexity decoding algorithms more efficiently by distributing data across multiple banks and stages, thereby reducing the memory footprint required for each individual processing element while maintaining overall processing capability.
3Reliability
If conventional LDPC decoding architecture is used, then decoding performance is maintained, but interconnection complexity increases
Solution Approach 1:
The interconnection network is segmented into multiple stages, with each stage handling connections between specific processing elements. This segmentation reduces the overall interconnection complexity by limiting the fan-out and fan-in requirements at each stage, while still maintaining the necessary data flow paths for accurate decoding performance through carefully designed connection patterns between stages.
Data Source
Figure 1A~1B
Figure 2~3
Figure 4
AI summary
An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.