LDPC Decoder Flag Memory Scheme for Power-Efficient Iterative Decoding
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Solution Overview
Problem
Low-density parity-check (LDPC) decoding processes consume high power due to frequent memory access, and reducing memory access can compromise error correction performance.
Innovation Solution
A decoder architecture with a main memory and a smaller flag memory, where flag encoding and decoding operations determine whether to store data in the main memory or flag memory, optimizing power consumption without degrading error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory access is reduced to save power, then power consumption decreases, but error correction performance deteriorates
Solution Approach 1:
The patent divides the intermediate value storage into two segments: a first memory for storing all intermediate values, and a second memory (flag memory) for storing only flag data that indicates whether flag encoding is successful. This segmentation allows the system to reduce access to the larger first memory while maintaining error correction capability through selective access based on flag status.
Solution Approach 2:
The patent extracts the critical error correction information (flag data) from the complete intermediate value set and stores it separately in a dedicated flag memory. This extraction allows the decoder to quickly determine whether full memory access is necessary, thereby reducing overall memory access frequency and power consumption while preserving error correction performance.
2Loss of energy
If the number of memory accesses is reduced, then power consumption decreases, but throughput decreases
Solution Approach 1:
The patent performs flag encoding operations and stores the results in advance in the flag memory before the actual decoding iterations begin. This preliminary action allows the decoder to quickly reference flag status during iterations without performing full memory accesses, thereby maintaining throughput while reducing power consumption.
Solution Approach 2:
The flag memory acts as an intermediary between the first memory and the decoding logic. By checking the flag memory first, the system can determine whether access to the first memory is necessary, thus mediating between the need for complete data access (throughput) and the desire to minimize access (power consumption).
Data Source
AI summary
A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.