LDPC Parity Group Interleaving for Robust Puncturing Order
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Solution Overview
Problem
Current signal transmitters and receivers in digital broadcasting face challenges in providing improved performance and versatility to meet the demands of high-definition digital television and portable broadcasting, particularly in terms of signal transmission and reception schemes.
Innovation Solution
A transmitter equipped with a Low Density Parity Check (LDPC) encoder, a parity permutator, and a puncturer that performs parity permutation by interleaving and puncturing parity bits, ensuring specific parity bits are positioned at predetermined locations and others are randomly placed, enhancing decoding characteristics and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are transmitted without permutation, then the transmission structure is simple, but decoding performance and error correction capability are insufficient
Solution Approach 1:
The patent applies preliminary action by performing parity permutation in advance before transmission. The transmitter reorders parity bits according to a predetermined pattern, placing some parity bits at specific positions and others in random positions. This pre-processing enables the receiver to achieve better decoding performance without adding complex real-time processing, as the permutation structure is established beforehand.
Solution Approach 2:
The patent segments the parity bits into different groups with different positioning strategies. Some parity bits are placed at predetermined positions while others are placed in random positions. This segmentation allows the system to optimize different portions of the parity bit sequence for different decoding requirements, improving overall decoding performance while maintaining manageable complexity.
2Productivity
If all parity bits are punctured, then the transmission efficiency increases, but error correction capability deteriorates
Solution Approach 1:
The patent applies local quality by treating different parity bits differently through selective puncturing. After permutation, some parity bits at predetermined positions are punctured while others in random positions are retained. This localized differentiation allows the system to remove redundant parity bits for efficiency while preserving critical parity bits for error correction, achieving both transmission efficiency and reliability.
Solution Approach 2:
The patent implements partial action by puncturing only a portion of the parity bits rather than all of them. The selective puncturing scheme removes some parity bits to improve transmission efficiency while retaining others to maintain error correction capability. This partial approach balances the trade-off between efficiency and reliability.
3Adaptability or versatility
If parity bits are randomly positioned, then the permutation flexibility increases, but the predictability for receiver synchronization decreases
Solution Approach 1:
The patent applies asymmetry by using an asymmetric positioning strategy where some parity bits are placed at predetermined positions and others at random positions. This asymmetric arrangement provides both flexibility and predictability - the predetermined positions offer synchronization reference points while the random positions provide permutation flexibility for performance optimization.
Data Source
AI summary
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.