LDPC Bit Group Interleaving for QPSK Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 7/15, using a specific permutation order for bit group-based interleaving, optimized for QPSK modulation, to effectively distribute burst errors in next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bit-by-bit interleaver is used in BICM systems, then flexibility in selecting modulation order and error correction code parameters is improved, but performance degrades rapidly due to burst errors in digital broadcast channels
Solution Approach 1:
The interleaver divides the codeword into multiple blocks and performs interleaving operations on each block separately. The codeword of length N is divided into N/M blocks of length M, where M is a parallel factor. This segmentation allows the system to maintain flexibility while distributing burst errors across multiple blocks, preventing catastrophic failure of the entire codeword.
Solution Approach 2:
The patent introduces a two-dimensional interleaving structure by organizing bits into rows and columns. The first interleaving operation arranges bits in a row-major fashion, while the second interleaving operation processes columns. This dimensional transformation effectively spreads burst errors across different spatial locations in the transmitted signal.
2Device complexity
If burst errors are not distributed, then system complexity is reduced, but error correction performance degrades rapidly
Solution Approach 1:
The interleaving process is segmented into multiple independent stages: block division, first interleaving, second interleaving, and deinterleaving. Each stage performs a specific function that contributes to burst error distribution without requiring complex overall architecture. The use of parallel factors M1 and M2 allows independent optimization of each segmentation dimension.
Solution Approach 2:
The patent introduces intermediate buffers and control logic that mediate between the simple input/output interfaces and the complex interleaving operations. These intermediaries manage the block division, row-column transformation, and reassembly processes, hiding the complexity from the system boundaries while maintaining simple external interfaces.
3Reliability
If an optimized bit interleaver is designed for specific LDPC code parameters and modulation order, then error correction performance is improved, but adaptability to different broadcasting standards is reduced
Solution Approach 1:
The interleaver is designed with configurable parameters including parallel factors M1 and M2, block length M, and code rate R. These parameters can be adjusted to match different LDPC code specifications and modulation schemes. The same fundamental interleaving structure works across multiple broadcasting standards by parameter configuration rather than requiring different hardware architectures.
Solution Approach 2:
The interleaver employs dynamic parameter selection where the parallel factors and block sizes are determined based on the input codeword length and desired code rate. The control logic dynamically adjusts the interleaving parameters to optimize performance for the specific transmission conditions and target broadcasting standard, making the system adaptable rather than fixed.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.