LDPC Group Interleaving for Reliable High-Order Modulation
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Solution Overview
Problem
In communication and broadcasting systems, high digital communication systems face challenges due to noise, fading, and inter-symbol interference, which affect data throughput and reliability, particularly in next-generation mobile communication and digital broadcasting. The performance of Low Density Parity Check (LDPC) codes is hindered by the complexity of mapping codeword bits onto high-order modulation bits.
Innovation Solution
A transmitting apparatus and method that includes an encoder for generating LDPC codewords, an interleaver for rearranging bit groups based on modulation order, and a modulator to generate modulation symbols, ensuring that bit groups are spaced or ordered optimally for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If LDPC codeword bits are mapped onto high order modulation bits using conventional methods, then the system can achieve high data throughput, but the performance deteriorates due to noise, fading, and inter-symbol interference
Solution Approach 1:
The LDPC codeword is divided into multiple bit groups, and each bit group is independently interleaved and mapped to modulation symbols. This segmentation allows for more flexible arrangement of bits to avoid mapping adjacent codeword bits to adjacent modulation symbol positions, thereby reducing inter-symbol interference and improving reliability while maintaining high data throughput
Solution Approach 2:
The patent applies preliminary interleaving operations on bit groups before mapping to modulation symbols. By pre-arranging the bit groups in an optimized sequence that considers the modulation order and symbol structure, the system prepares the data in advance to mitigate the effects of noise and fading during transmission, thus improving reliability without sacrificing throughput
2Reliability
If bit groups are interleaved and divided based on modulation order, then mapping performance is improved, but the device complexity increases
Solution Approach 1:
The interleaver is designed to operate on bit groups rather than individual bits, and the bit groups are processed in a structured manner based on modulation order. This segmentation approach simplifies the interleaving logic compared to bit-level processing, as entire groups can be rearranged as units, reducing the computational complexity and device requirements while still achieving improved mapping performance
Solution Approach 2:
The patent applies interleaving selectively to bit groups rather than all bits uniformly, and the degree of interleaving is adjusted based on the modulation order. For higher order modulations where performance improvement is more critical, more aggressive interleaving is applied, while for lower order modulations, simpler mapping is used. This partial application of interleaving optimizes the balance between performance improvement and device complexity
Data Source
AI summary
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.