LDPC Bit Group Interleaving for Decoding-Stable Symbol Mapping

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Solution Overview

Problem

There is a need for improved decoding and receiving performance in digital broadcasting services, particularly in high-quality digital television and portable multimedia systems, where existing methods do not adequately support various receiving methods and fail to provide enhanced user experiences.

Innovation Solution

A transmitting apparatus and method that uses an LDPC codeword encoder, interleaver, and modulator to map bits from a predetermined bit group onto a modulation symbol, employing a parity interleaver, group interleaver, and block interleaver to optimize bit arrangement and transmission, specifically using equations to determine the interleaving order based on the LDPC codeword length, modulation method, and code rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional transmission methods are used, then device complexity is reduced, but decoding and receiving performance deteriorates

Engineering Contradiction:
Improvedecoding and receiving performanceVSAvoidtransmission processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC codeword is divided into multiple bit groups, and each bit group is separately interleaved and mapped to modulation symbols. This segmentation allows for more granular control of bit arrangement to improve decoding performance while managing complexity through modular processing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Parity bits are interleaved and bit groups are rearranged before modulation and transmission. This preliminary arrangement of bits according to specific patterns (using equations for interleaving order) prepares the data to enhance receiving performance during decoding without adding complex real-time processing

Inventive Principle:
Principle #10Preliminary action

2Reliability

If bit groups are rearranged and interleaved, then receiving performance is improved, but processing time increases

Engineering Contradiction:
Improvereceiving performanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The transmission processing is divided into separate stages: parity interleaving, group-wise rearrangement, and modulation mapping. Each stage processes specific portions of the data independently, allowing for optimized processing time while achieving the performance benefits of complex bit arrangement

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interleaving order and bit group arrangement are dynamically determined based on equations that consider LDPC codeword length, modulation method, and code rate. This dynamic adaptation allows the system to optimize processing efficiency for different transmission conditions while maintaining improved receiving performance

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10396819B1Transmitter apparatus and bit interleaving method thereof
Publication Date: 2019.08.27 SAMSUNG ELECTRONICS CO LTD
  • US10396819B1 patent drawing
  • US10396819B1 patent drawing
  • US10396819B1 patent drawing

AI summary

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.