LDPC Group Interleaving for Noise-Resistant Symbol Mapping
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Solution Overview
Problem
Current communication systems face challenges in overcoming noise, fading, and inter-symbol interference, particularly in high data throughput applications like next-generation mobile communication and digital broadcasting, where existing error-correction codes are inefficient.
Innovation Solution
A transmitting apparatus and method that employs LDPC encoding, interleaving, and modulation to effectively map LDPC codeword bits onto high-order modulation symbols, utilizing a combination of group and block interleavers to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing error-correction codes are used in high-order modulation schemes, then data throughput can be increased, but performance deteriorates due to noise, fading, and inter-symbol interference
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups and applies different interleaving strategies to different segments. The group interleaver divides the codeword into N groups and rearranges them, while the block interleaver further processes each group. This segmentation allows the system to handle noise and interference more effectively by distributing adjacent bits across different modulation symbols, preventing catastrophic failures from concentrated errors.
Solution Approach 2:
The patent applies preliminary interleaving operations before modulation to pre-distribute bits in a way that anticipates and mitigates future interference patterns. By performing group interleaving and block interleaving before the data is modulated onto high-order symbols, the system proactively prepares the bit sequence to resist noise, fading, and inter-symbol interference that will occur during transmission.
2Ease of manufacture
If LDPC codeword bits are directly mapped onto high-order modulation bits, then implementation is simple, but performance is insufficient due to poor mapping efficiency
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups and applies a two-stage interleaving process: group interleaving that rearranges entire groups, and block interleaving that processes bits within groups. This segmentation transforms the simple but poor direct mapping into a structured multi-stage process that maintains implementation feasibility while dramatically improving mapping performance and resistance to interference.
Solution Approach 2:
The patent introduces an additional dimension of processing by applying interleaving operations across multiple levels (group level and block level) rather than simple sequential mapping. This multi-dimensional approach to bit arrangement optimizes the distribution of bits across modulation symbols, achieving near-Shannon-limit performance while maintaining practical implementation complexity.
Data Source
AI summary
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.