LDPC Group-Wise Interleaving for Lower Error-Floor Transmission
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Solution Overview
Problem
Current data transmission using LDPC codes faces challenges in maintaining excellent communication quality, particularly in ensuring robust error correction and preventing the error floor phenomenon associated with turbo codes.
Innovation Solution
The implementation of a data processing device and method that performs LDPC encoding with a specific parity check matrix, group-wise interleaving, and mapping to 16 signal points, utilizing a code length of 16200 bits and encoding rates of 10/15 and 12/15, to enhance communication quality by optimizing bit group interleaving and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC encoding is performed with standard parameters, then data transmission can be implemented, but communication quality and error correction performance are insufficient
Solution Approach 1:
The patent applies parameter changes by optimizing specific LDPC code parameters including code length (16200 bits), encoding rates (10/15 and 12/15), and bit group size (360 bits). These parameter adjustments improve communication quality and error correction performance while maintaining manageable system complexity through standardized configurations.
Solution Approach 2:
The patent implements segmentation through group-wise interleaving that divides the LDPC code into multiple bit groups of 360 bits each. This segmentation approach improves error correction by distributing errors across different groups and enables more efficient processing while maintaining overall code performance.
2Reliability
If group-wise interleaving is performed with optimized bit group sequence, then error floor phenomenon is reduced, but processing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-defining the optimal bit group sequence (27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, 38) for group-wise interleaving. This predetermined sequence eliminates the need for real-time optimization calculations, reducing processing complexity while maintaining excellent error correction capability and preventing error floor phenomenon.
3Reliability
If code length is increased to improve error correction, then performance approaches Shannon limit, but transmission efficiency decreases
Solution Approach 1:
The patent optimizes the balance between reliability and productivity by selecting a code length of 16200 bits, which provides excellent error correction capability approaching the Shannon limit while maintaining reasonable transmission efficiency. The encoding rates of 10/15 and 12/15 further optimize this balance by providing different trade-offs between redundancy and data throughput.
Solution Approach 2:
The patent divides the 16200-bit code into 45 bit groups of 360 bits each, enabling efficient processing and transmission. This segmentation allows the system to handle the long code length in manageable units, improving both error correction performance and transmission efficiency through structured processing.
Data Source
AI summary
The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.