LDPC Parity Group Interleaving for Balanced Bit Puncturing

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Solution Overview

Problem

Current digital broadcasting systems face challenges in providing improved performance and efficiency in signal transmission and reception, particularly in high-definition digital TV and portable broadcasting, due to limitations in existing transmitter and receiver technologies.

Innovation Solution

A transmitter is designed with a Low Density Parity Check (LDPC) encoder, a parity permutator, and a puncturer to perform parity permutation on parity bits, specifically puncturing certain parity bits and rearranging them through group-wise interleaving, to enhance decoding performance and adapt to various receiving schemes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all parity bits are transmitted without puncturing, then decoding reliability is improved, but transmission efficiency and bandwidth utilization deteriorate

Engineering Contradiction:
Improvedecoding reliabilityVSAvoidtransmission efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and removes specific parity bits from the transmitted signal through puncturing. By selectively removing certain parity bits (those at positions that are multiples of 360 in the group-wise interleaved sequence) while retaining others, the system achieves a balance between maintaining decoding reliability and improving transmission efficiency by reducing redundant information transmission.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If parity bits are punctured to improve transmission efficiency, then bandwidth utilization is improved, but decoding performance deteriorates

Engineering Contradiction:
Improvebandwidth utilizationVSAvoiddecoding performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by treating different parity bits differently through selective puncturing. Instead of uniformly puncturing all or none of the parity bits, the system applies a specific puncturing pattern based on group-wise interleaving, where only certain parity bits (at positions that are multiples of 360) are removed. This localized differentiation maintains decoding performance while improving bandwidth utilization.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs group-wise interleaving of parity bits before puncturing. This preliminary rearrangement of parity bits ensures that the puncturing operation removes only specific bits that are less critical for decoding, thereby maintaining decoding performance even after puncturing. The preliminary interleaving action prepares the parity bits in an optimal sequence for selective removal.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If conventional transmission schemes are used, then system simplicity is maintained, but adaptability to various receiving schemes deteriorates

Engineering Contradiction:
Improveadaptability to receiving schemesVSAvoidtransmitter structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the parity bits into different groups through group-wise interleaving, where each group contains 360 bits. This segmentation allows the system to apply different processing (puncturing or retention) to different segments, providing adaptability to various receiving schemes. The segmented structure enables flexible configuration without requiring complete redesign of the transmission system.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10554222B2Transmitter and parity permutation method thereof
Publication Date: 2020.02.04 SAMSUNG ELECTRONICS CO LTD
  • US10554222B2 patent drawing
  • US10554222B2 patent drawing
  • US10554222B2 patent drawing

AI summary

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.