Partial Parallel LDPC Hard Decoder With Single-Cycle Syndrome Updates
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Solution Overview
Problem
Conventional partial parallel hard decoders for low-density parity-check codes face a trade-off between throughput and area efficiency, with high throughput implementations occupying significant area and low area implementations resulting in decreased throughput.
Innovation Solution
A high throughput and area efficient partial parallel hard decoder design that rearranges codeword bits, iteratively updates them, and generates syndrome values over a single cycle of a clock signal, allowing for simultaneous updating and validation of codeword bits, while storing and retrieving updated values efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If codeword bits are updated over multiple cycles with syndrome values generated exclusively after all updates, then the decoder occupies significant area, but the throughput is significantly reduced
Solution Approach 1:
The patent segments the decoding process into multiple pipelines operating in parallel. Different sets of codeword bits are updated and validated in different cycles simultaneously, allowing syndrome generation to overlap with codeword updates. This segmentation enables the decoder to achieve high throughput without requiring all resources to be available simultaneously, thus reducing area occupancy.
Solution Approach 2:
The patent performs preliminary actions by pre-organizing codeword bits into multiple sets before decoding begins. The syndrome generator is prepared to process different bit sets in different cycles, and the memory structures are pre-configured to support this pipelined operation. This preliminary organization enables efficient resource utilization and high throughput without requiring excessive area.
2Productivity
If all codeword bits are updated before generating syndrome values, then the decoder structure is simplified, but the decoding process takes multiple cycles reducing throughput
Solution Approach 1:
The patent implements continuity of useful action by maintaining an overlapping pipeline where syndrome generation continues even as new codeword bits are being updated. The syndrome generator does not wait for complete codeword updates but processes available bits in each cycle, ensuring continuous productive operation. This eliminates idle cycles and maximizes throughput while keeping the decoder structure manageable.
Solution Approach 2:
The patent introduces dynamic operation by allowing the syndrome generation process to adapt to the current state of codeword updates. Different pipelines operate at different stages of completion, and the system dynamically manages which bits are being updated versus which are being validated in each cycle. This dynamic approach enables high throughput without requiring all bits to be updated synchronously, reducing overall decoding time.
Data Source
AI summary
A hard decoder includes an input data handler that receives and rearranges a low-density parity-check (LDPC) codeword, and a variable node updater that iteratively updates the rearranged LDPC codeword to generate an updated LDPC codeword during each decoding iteration of the rearranged LDPC codeword. The hard decoder further includes a syndrome generator that generates a syndrome vector associated with the updated LDPC codeword of each decoding iteration. During each decoding iteration, the rearranged LDPC codeword is updated based on a threshold value and the syndrome vector associated with the updated LDPC codeword of a previous decoding iteration and a validity of the updated LDPC codeword of the previous decoding iteration. The hard decoder further includes an output data handler that extracts a message from the updated LDPC codeword that is valid and outputs the extracted message.