LDPC Index Matching for Fewer Min-Sum Decoder Iterations
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Solution Overview
Problem
Min-sum decoders in LDPC error correction often inaccurately correct bits during iterations, necessitating excessive iterations and reducing the efficiency of memory systems like SSDs, particularly in high RBER environments such as QLC NAND chips.
Innovation Solution
Implementing a hybrid LDPC method that combines min-sum and self-corrected min-sum algorithms, adjusting variable node data based on specific conditions, and using index matching to enhance error correction accuracy and reduce iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If min-sum algorithm is used for error correction in LDPC codes, then error correction capability is provided, but inaccurate bit corrections occur during iterations requiring excessive iterations
Solution Approach 1:
The patent implements feedback mechanisms where check nodes provide feedback information to variable nodes about the reliability of received messages. This feedback allows the decoder to identify and correct inaccurate bit corrections by adjusting variable node values based on check node feedback, thereby improving error correction capability while reducing the number of iterations needed.
Solution Approach 2:
The patent changes parameters such as threshold values and update rules dynamically during the decoding process. By adjusting these parameters based on the decoding state and error patterns, the system optimizes the balance between correction accuracy and iteration efficiency, resolving the contradiction between reliability and productivity.
2Measurement precision
If multiple iterations are implemented to correct inaccurate bit corrections, then error correction accuracy is improved, but decoding time and complexity increase
Solution Approach 1:
The patent performs preliminary actions by pre-calculating threshold values and preparing check node feedback mechanisms before the actual decoding process. This preliminary preparation enables more efficient iterations during decoding, reducing the total time required while maintaining high accuracy through the pre-established correction frameworks.
Solution Approach 2:
The patent introduces dynamic adjustment of decoding parameters and iteration strategies based on real-time decoding progress and error patterns. This dynamic approach allows the system to adapt the number and nature of iterations needed, reducing decoding time when fewer corrections are required while maintaining accuracy when necessary.
3Reliability
If variable node data is selectively set to 0 to adjust messages, then error correction strength is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by selectively modifying variable node data only in specific cases where conditions are met (such as when check node feedback indicates unreliable messages). This localized adjustment approach improves error correction strength in problematic areas without requiring complex modifications throughout the entire decoding system, thereby managing device complexity.
Solution Approach 2:
The patent changes parameters such as variable node values and message transmission rules dynamically based on decoding conditions. By adjusting these parameters only when necessary rather than using complex fixed rules, the system improves error correction strength while keeping the overall algorithm complexity manageable through simple conditional logic.
Data Source
AI summary
This application is directed to data validation in an electronic device. The electronic device identifies a set of check nodes associated with a first variable node that corresponds to a data bit in a block of data, and obtains check node data from each of the set of check nodes. Each check node is associated with a set of respective variable nodes including the first variable node, and the check node data identifies at least a respective target node providing the smallest variable node data among the respective variable nodes. The electronic device identifies a subset of check nodes for each of which the check node data identifies the first variable node as the respective target node, determines that the subset of check nodes includes a first number of check nodes, and determines variable node data of the first variable node based on the first number.