LDPC Decoder Indexed Messages for Low-Bit-Width Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Low-density parity check (LDPC) decoders face issues with degraded performance due to finite precision in message representation, leading to saturation and increased power/energy consumption, especially in min-sum algorithms used in data storage and communication systems.
Innovation Solution
The implementation of an LDPC decoder with indexed messages allows n-bit indices to represent values ranging from 0 to 2^m-1, using message mappers to scale values within VNUs and CNUs, reducing the bit width requirements while maintaining performance through VNU scaling and inverse mappers, thereby reducing power/energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If finite precision message representation is used in LDPC decoders, then device complexity and power consumption are reduced, but decoding performance degrades due to saturation
Solution Approach 1:
The patent transforms the message representation from direct binary values to indexed values that reference a larger numerical range. Instead of using m bits to represent values up to 2^m-1 directly, the system uses n bits (where n < m) to index into a pre-defined set of 2^n values that can represent up to 2^m-1. This dimensional transformation allows reduced bit-width messages to carry equivalent information content, improving energy efficiency while maintaining decoding performance.
Solution Approach 2:
The patent introduces message mappers as intermediary components that translate between indexed message representations and the actual numerical values needed for decoding operations. These mappers act as mediators that allow the decoder to work with compact indexed representations internally while maintaining compatibility with the full-precision mathematical operations required for accurate decoding, thus resolving the conflict between low bit-width and high performance.
2Use of energy by moving object
If reduced bit width messages are used, then power consumption decreases, but message precision is lost leading to saturation
Solution Approach 1:
The patent changes the parameter representation by mapping n-bit indices to values in a larger range (0 to 2^m-1 where m > n). This parameter transformation allows the system to use fewer bits for message transmission while the mapped values maintain the precision required for accurate decoding. The message mappers implement this parameter change by selecting from pre-computed lookup tables that associate each n-bit index with its corresponding high-precision numerical value.
3Device complexity
If n-bit indices represent values up to 2^m-1, then device complexity is reduced, but implementation complexity increases due to mapping requirements
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing the mapping relationships between n-bit indices and their corresponding numerical values in lookup tables during the decoder design phase. This pre-computation eliminates the need for complex real-time calculation logic during decoding operations. The message mappers simply retrieve pre-computed values from these lookup tables based on the received indices, significantly simplifying the hardware implementation while maintaining the ability to represent high-precision values.
Data Source
AI summary
A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.