LDPC Soft Decoding Inter-Cell Interference Mitigation

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Solution Overview

Problem

Flash memory devices face performance degradation due to inter-cell interference (ICI), which is exacerbated by increasing cell density and bit programming, leading to decoding errors and reduced system reliability.

Innovation Solution

The implementation of an ICI algorithm module that generates log-likelihood ratio (LLR) values based on the bottom programming level of adjacent cells, using multiple read cycles and LLR mapping tables to mitigate ICI effects, thereby improving decoding accuracy and reducing error rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If cell density and bit programming are increased to improve storage capacity, then storage capacity is improved, but inter-cell interference increases leading to decoding errors and reduced reliability

Engineering Contradiction:
Improvestorage capacityVSAvoiddecoding reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the decoding process into multiple read cycles, where each cycle reads at a different reference voltage level. This segmentation allows the system to extract multiple bits of information from each cell while accounting for ICI effects at different voltage thresholds, thereby maintaining decoding reliability despite increased cell density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by conducting multiple read cycles before final decoding, where each read cycle gathers information about the cell state under different reference voltage conditions. This preliminary data collection enables the system to calculate LLR values that compensate for ICI effects, ensuring reliable decoding even with high cell density

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If multiple read cycles are performed to mitigate ICI effects, then decoding accuracy is improved, but read time and energy consumption increase

Engineering Contradiction:
Improvedecoding accuracyVSAvoidread time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by performing a limited number of read cycles (typically 2-3 cycles) rather than exhaustive readings. This partial action is sufficient to capture the necessary information for accurate LLR calculation while avoiding excessive read time, achieving an optimal balance between decoding accuracy and time consumption

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9117529B2Inter-cell interference algorithms for soft decoding of LDPC codes
Publication Date: 2015.08.25 WESTERN DIGITAL TECHNOLOGIES INC
  • US9117529B2 patent drawing
  • US9117529B2 patent drawing
  • US9117529B2 patent drawing

AI summary

Aspects of the subject technology relate to a method for reading information stored in a flash memory device. In some implementations, the method can include steps including, obtaining a first read signal of a first cell, wherein the first cell is located in a first word line and a first bit line in the flash memory device, obtaining a programming level of a second cell, wherein the second cell is located in a second word line and the first bit line, and wherein the second word line is adjacent to the first word line. In certain aspects, the method may further comprise steps for obtaining decoding information for the first cell based on the programming level of the second cell. A data storage system and article of manufacture are also provided.