Group-Based LDPC Bit Interleaver for 1024-Symbol BICM
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 4/15, using 1024-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, effectively distributing burst errors and optimizing performance for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The bit interleaver divides the LDPC codeword into multiple bit groups (180 groups of 360 bits each) and processes them separately through permutation. This segmentation allows the system to handle burst errors more effectively by distributing them across different bit groups, thereby improving reliability without requiring a completely different system architecture.
Solution Approach 2:
The interleaver applies a predetermined permutation sequence to the bit groups before transmission. This preliminary arrangement of bits ensures that when burst errors occur during transmission, they are distributed across different original positions after deinterleaving, preventing concentrated error patterns that would degrade performance.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the system loses flexibility in adapting to different configurations
Solution Approach 1:
The interleaver design uses parameters (such as bit group size of 360 bits and number of groups of 180) that are specifically optimized for LDPC codes with length 64800 and code rate 4/15, combined with 1024-QAM modulation. These parameter settings are configured to achieve optimal error correction performance for this specific combination of code and modulation, rather than using a generic design that would work adequately across all configurations.
3Reliability
If burst errors are not distributed, then the interleaver structure remains simple, but error correction performance degrades rapidly
Solution Approach 1:
The interleaver operates on bit groups rather than individual bits, introducing a group-level dimension to the interleaving process. Each bit group contains 360 bits, and the permutation operates at this group level according to a predefined sequence. This dimensional approach to interleaving effectively distributes burst errors while maintaining a manageable structure.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.