LDPC Bit Interleaver Permutation for 1024-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 4/15, using 1024-symbol mapping, is designed to effectively distribute burst errors by interleaving LDPC codewords on a bit group basis with a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and applies permutation-based interleaving to rearrange these bit groups. This segmentation approach distributes burst errors across different bit groups, preventing concentrated error patterns that would degrade system performance while maintaining the bandwidth efficiency of BICM transmission.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then it can effectively distribute burst errors, but the device complexity increases due to the need for optimized design
Solution Approach 1:
The patent employs parameter-based permutation tables that are specifically optimized for given modulation orders (e.g., 1024-QAM) and LDPC code parameters (length 64800, code rate 4/15). By changing and optimizing these parameters for specific system configurations, the interleaver achieves effective burst error distribution without requiring overly complex structural designs, thus balancing reliability improvement with manageable device complexity.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.