LDPC Bit Interleaver Layout for 1024-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 3/15, employing 1024-symbol mapping, is designed to effectively distribute burst errors by interleaving the LDPC codeword on a bit group basis using a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and applies separate interleaving operations to each group using different permutation orders. This segmentation allows the system to distribute burst errors across multiple groups, preventing any single group from suffering catastrophic error concentration, thereby improving reliability without requiring a completely new interleaver architecture
Solution Approach 2:
The patent applies different permutation orders to different bit groups based on their specific positions and characteristics. Each bit group undergoes a tailored interleaving operation optimized for its local requirements, allowing the system to address burst error patterns more effectively in different parts of the codeword while maintaining overall system performance
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the system loses flexibility in adapting to different broadcasting standards
Solution Approach 1:
The patent employs dynamic permutation orders that can be adjusted based on the specific modulation order (e.g., 1024-QAM) and LDPC code parameters (length 64800, code rate 3/15). The interleaver structure itself remains flexible, allowing the permutation sequences to be reconfigured for different broadcasting standards and operational conditions, thus maintaining both optimized performance and adaptability
Solution Approach 2:
The patent changes the permutation order parameters based on the specific modulation and coding configuration being used. By adjusting these parameters rather than redesigning the entire interleaver, the system can optimize performance for each specific standard (e.g., ATSC 3.0) while maintaining the same underlying interleaver structure, preserving versatility
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.