LDPC Bit Interleaver Layout for Burst-Error-Resilient 16-Symbol Mapping

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.

Innovation Solution

A bit interleaver is designed for an LDPC coder with a length of 16200 and code rate of 4/15, using a processor to generate an interleaved codeword on a bit group basis, with a specific permutation order for effective distribution of burst errors, and a modulator performing 16-symbol mapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation

Engineering Contradiction:
Improveperformance reliabilityVSAvoidinterleaver design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The codeword is divided into multiple bit groups, and interleaving is performed on a bit group basis rather than individual bits. This segmentation approach effectively distributes burst errors across different bit groups while maintaining a relatively simple interleaver structure optimized for specific LDPC code rates and modulation orders

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interleaver design is optimized by changing parameters such as the bit group size, permutation order, and interleaving pattern to match specific LDPC code rates (e.g., 4/15) and modulation orders (e.g., 16-QAM). This parameter optimization improves error distribution effectiveness without requiring complex adaptive structures

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the bit interleaver is optimized for specific modulation order and code rate, then error correction performance is improved, but the system loses flexibility in adapting to different broadcasting standards

Engineering Contradiction:
Improveerror correction performanceVSAvoidmodulation and code rate adaptability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The interleaver design achieves multi-functionality by implementing a unified bit group-based interleaving structure that can be configured for different LDPC code rates and modulation orders. The same fundamental interleaving mechanism works across multiple broadcasting standards (DVB-T2, DVB-NGH, ATSC 3.0) by adjusting parameters like bit group size and permutation sequences rather than requiring entirely different interleaver designs

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If burst errors are not properly distributed, then the transmission system can maintain a simple structure, but performance degrades rapidly in noisy channels

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bit interleaver performs preliminary distribution of bit groups before modulation and transmission. By pre-arranging bit groups in an interleaved sequence based on optimized permutation orders, the system proactively prepares for potential burst errors, ensuring that even if errors occur, they will be distributed across different code blocks rather than concentrated in one location

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10944434B2Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 16-symbol mapping, and bit interleaving method using same
Publication Date: 2021.03.09 ELECTRONICS & TELECOMM RES INST
  • US10944434B2 patent drawing
  • US10944434B2 patent drawing
  • US10944434B2 patent drawing

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.