Bit-Group LDPC Interleaver for 256-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and a code rate of 10/15, using 256-symbol mapping, which interleaves the LDPC codeword on a bit group basis according to a specific permutation order, effectively distributing burst errors and enhancing error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (e.g., 45 bit groups of 360 bits each) and applies independent interleaving operations to each group using different permutation orders. This segmentation allows the system to distribute burst errors across multiple groups while maintaining a structured approach that balances performance improvement with implementation complexity
Solution Approach 2:
The patent applies different interleaving strategies to different parts of the codeword. Specifically, information bit groups and parity bit groups are interleaved differently, with information bits using one permutation order and parity bits using another. This local differentiation optimizes error distribution for each segment's specific requirements
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance improves, but the system loses flexibility in selecting different modulation and coding schemes
Solution Approach 1:
The patent implements a dynamic interleaving scheme where the permutation orders and bit group configurations are adjusted based on the selected modulation order and LDPC code parameters. The system can adaptively change the interleaving depth, group size, and permutation patterns to match different transmission conditions and performance requirements, maintaining both optimization and flexibility
3Reliability
If burst errors are not distributed, then the interleaver structure remains simple, but the error correction code performance degrades rapidly
Solution Approach 1:
The patent extends the interleaving operation from simple bit-level shuffling to a two-dimensional structure involving bit groups and permutation orders. By organizing bits into groups and applying permutations across group boundaries, the system achieves superior error distribution in both the bit dimension and the group dimension, effectively breaking up burst errors while maintaining structural organization
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.