Bit-Group LDPC Interleaver for 4096-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 64800 and code rate of 5/15, using 4096-symbol mapping, is designed to effectively distribute burst errors by interleaving LDPC codewords on a bit group basis, with a specific permutation order, suitable for next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent segments the LDPC codeword into multiple bit groups (e.g., 180 bit groups of 360 bits each) and applies permutation to each bit group independently. This segmentation allows the interleaver to effectively distribute burst errors across different bit groups while maintaining a manageable structure that doesn't excessively increase device complexity
Solution Approach 2:
The patent optimizes specific parameters including the permutation order sequence, bit group size (360 bits), and number of bit groups (180 groups) to achieve optimal performance for 4096-QAM modulation with LDPC code rate 5/15. These parameter changes are tailored to resolve the contradiction between reliability and complexity for specific system configurations
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then performance improves, but the adaptability to different system configurations decreases
Solution Approach 1:
The patent establishes optimized parameter sets for specific configurations (e.g., 4096-QAM, LDPC 64800 length, code rate 5/15, 360-bit groups, 180 groups total) to achieve peak performance. The methodology allows system designers to select appropriate parameter sets based on their specific modulation and coding requirements, balancing optimization with adaptability through configurable parameters
3Reliability
If burst errors are not distributed, then the interleaver structure remains simple, but error correction capability deteriorates rapidly
Solution Approach 1:
By dividing the codeword into 180 bit groups and applying permutation across these groups, the system achieves effective burst error distribution. Errors that would otherwise concentrate in contiguous segments are dispersed across multiple bit groups, enhancing error correction capability while keeping the interleaving structure computationally manageable
Solution Approach 2:
The bit group structure acts as an intermediary between the raw LDPC codeword and the final modulated signal. This intermediate organization into 360-bit groups with specific permutation patterns enables effective error distribution without requiring overly complex direct interleaving of all 64800 bits simultaneously
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.