LDPC Bit Interleaver Permutation for 64-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and code rate of 3/15, using 64-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, employing a specific permutation order to effectively distribute burst errors and improve error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in the channel cause rapid performance degradation
Solution Approach 1:
The patent divides the LDPC codeword into multiple bit groups (e.g., 45 bit groups of 360 bits each) and applies separate permutation operations to each group. This segmentation allows the interleaver to effectively distribute burst errors across different groups while maintaining a manageable design complexity through standardized group processing
Solution Approach 2:
The patent optimizes the permutation order parameters specifically for LDPC codes with length 16200 and code rate 3/15, combined with 64-symbol mapping. By tailoring the permutation parameters to specific code and modulation parameters, the system achieves superior error correction performance without requiring overly complex adaptive structures
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance improves, but the adaptability to different configurations decreases
Solution Approach 1:
The patent employs parameterized permutation orders that can be configured for different LDPC code lengths, code rates, and modulation orders. The bit group size and permutation sequences are defined as configurable parameters, allowing the same interleaver structure to be optimized for various BICM configurations including different code rates and modulation schemes
Solution Approach 2:
The interleaver design uses a universal bit group-based permutation structure that can handle multiple LDPC code configurations and modulation orders. By defining the permutation operation in terms of configurable parameters rather than fixed values, the same hardware/software structure serves multiple functions across different system configurations
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.