LDPC Bit Interleaving Structure for High-Order Modulation Reliability
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Solution Overview
Problem
In communication and broadcasting systems, high digital communication systems face challenges due to noise, fading, and inter-symbol interference, which affect data throughput and reliability, particularly in next-generation mobile communication and digital broadcasting. The performance of Low Density Parity Check (LDPC) codes is hindered by the complexity of mapping codeword bits onto high-order modulation bits.
Innovation Solution
A transmitting apparatus and method that includes an encoder for generating LDPC codewords, an interleaver to rearrange bit groups based on modulation order, and a modulator to generate modulation symbols, using a combination of group and block interleavers to optimize the mapping of LDPC codeword bits onto modulation symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codeword bits are mapped onto high-order modulation bits using conventional methods, then the system complexity is reduced, but the communication reliability and throughput deteriorate due to noise and interference
Solution Approach 1:
The LDPC codeword is divided into multiple bit groups, and each bit group is separately mapped to modulation symbols. This segmentation allows for more flexible and optimized mapping strategies that improve reliability while managing complexity through modular processing.
Solution Approach 2:
The patent introduces a two-dimensional mapping structure where bit groups are arranged in rows and columns, with different mapping patterns applied along different dimensions. This dimensional approach enables better exploitation of code structure to improve communication reliability under high-order modulation.
2Productivity
If high-order modulation schemes are used to increase data throughput, then the productivity increases, but the system becomes more susceptible to noise, fading, and inter-symbol interference
Solution Approach 1:
Different mapping patterns are applied to different bit groups within the same codeword, allowing local optimization of mapping quality. This enables the system to achieve high throughput through high-order modulation while maintaining reliability through localized adaptive mapping strategies.
Solution Approach 2:
The patent employs multiple mapping patterns that can be selected or switched based on channel conditions and modulation order. By changing mapping parameters dynamically, the system optimizes the trade-off between throughput and reliability for high-order modulation schemes.
3Reliability
If iterative decoding based on sum-product algorithm is applied to achieve channel capacity performance, then the reliability improves, but the computational complexity and processing time increase
Solution Approach 1:
The patent performs preliminary interleaving and structured arrangement of LDPC codeword bits before transmission. This preliminary action facilitates more efficient decoding by pre-organizing the data in a manner that optimizes the iterative decoding process, reducing processing time while maintaining reliability.
Data Source
AI summary
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.