LDPC Bit Interleaver Layout for QPSK Burst Error Dispersion
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 7/15, using a specific permutation order for bit group-based interleaving, optimized for QPSK modulation, to effectively distribute burst errors in broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bit-by-bit interleaver is used in BICM systems, then the system can provide high-level flexibility and bandwidth efficiency, but burst errors occurring in the channel cause rapid performance degradation
Solution Approach 1:
The patent segments the bit stream into groups of bits (e.g., 360 bits per group for LDPC code length 64800) and applies permutation-based interleaving within each group. This segmentation allows the system to maintain flexibility while distributing burst errors across multiple bit groups, preventing concentrated error patterns that would degrade performance.
Solution Approach 2:
The patent introduces a permutation dimension to the bit interleaving process by applying specific permutation orders to bit groups. This transforms the simple sequential bit stream into a multi-dimensional structure where bits are rearranged according to predefined permutation patterns, effectively dispersing burst errors without compromising system flexibility.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance is improved, but the device complexity increases
Solution Approach 1:
The patent optimizes the interleaver by changing specific parameters such as the permutation order and bit group size to match the LDPC code parameters (length 64800, code rate 7/15) and modulation scheme (QPSK). These parameter adjustments are carefully selected to improve error correction performance while maintaining a relatively simple interleaver structure that can be efficiently implemented.
Solution Approach 2:
The patent applies different permutation patterns to different bit groups based on their specific positions and characteristics. Instead of using a uniform interleaving approach, the system tailors the permutation order to local requirements, optimizing error distribution for each segment while keeping the overall system complexity manageable through standardized local operations.
3Reliability
If burst errors are distributed through bit group-based interleving, then performance degradation is prevented, but the processing time and complexity of the interleaving operation increase
Solution Approach 1:
The patent employs pre-defined permutation orders that are calculated and stored in advance. During the interleaving operation, the system simply applies these predetermined patterns to bit groups rather than computing new permutations in real-time. This preliminary preparation significantly reduces the processing time required during actual transmission while still achieving effective burst error distribution.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.