LDPC Bit Interleaver Layout for QPSK Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 7/15, using a specific permutation order for bit group-based interleaving, optimized for QPSK modulation, to effectively distribute burst errors in next-generation broadcasting systems like ATSC 3.0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a bit-by-bit interleaver is used in BICM systems, then the system can provide bandwidth-efficient transmission and flexibility in modulation order and code parameters, but the system suffers from rapid performance degradation due to burst errors in digital broadcast channels
Solution Approach 1:
The interleaver divides the codeword into multiple bit groups, where each bit group contains a specific number of bits (e.g., 360 bits). This segmentation allows the system to process and distribute burst errors across multiple bit groups rather than affecting all bits uniformly, thereby maintaining bandwidth efficiency while improving reliability against burst errors.
Solution Approach 2:
The patent introduces a two-dimensional interleaving structure by organizing bits into groups and applying permutation operations across these groups. This dimensional transformation converts a simple sequential interleaving into a structured multi-dimensional arrangement, enabling effective burst error distribution while preserving the flexibility of BICM systems.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then the system can achieve excellent performance, but the device complexity increases due to the need for optimized designs
Solution Approach 1:
The patent provides specific optimization for LDPC codes with length 64800 and code rate 7/15, combined with QPSK modulation. By fixing these parameters, the interleaver design achieves excellent performance for this specific configuration without requiring complex adaptive mechanisms. The permutation order and bit group size are specifically tuned for these parameters, reducing design complexity while maintaining high performance.
3Device complexity
If burst errors are not appropriately distributed, then the system structure remains simple, but the system suffers from rapid performance degradation
Solution Approach 1:
The interleaver performs preliminary distribution of burst errors across bit groups before transmission. By pre-organizing the codeword bits into groups and applying permutation operations in advance, the system prepares the data structure to withstand burst errors without requiring complex real-time processing during transmission, thus maintaining structural simplicity while improving reliability.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.